UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 638

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

638
16-bit data
transfer
8-bit
operation
Notes 1.
Remarks 1.
Instruction
Group
2.
3.
4.
2.
MOVW
XCHW
ADD
ADDC
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Only when rp = BC, DE or HL
Except “r = A”
Mnemonic
One instruction clock cycle is one cycle of the CPU clock (f
control register (PCC).
This clock cycle applies to the internal ROM program.
rp, #word
saddrp, #word
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
sfrp, AX
AX, rp
rp, AX
AX, !addr16
!addr16, AX
AX, rp
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
CHAPTER 26 INSTRUCTION SET
Note 3
Note 3
Note 3
Note 4
Note 4
User’s Manual U17554EJ4V0UD
Bytes
3
4
4
2
2
2
2
1
1
3
3
1
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
10
10
6
8
−
6
6
−
−
4
4
4
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clocks
Note 2
10
10
12
12
−
8
8
8
8
−
−
−
−
8
−
−
5
9
5
9
9
9
−
8
−
−
5
9
5
9
9
9
rp ← word
(saddrp) ← word
sfrp ← word
AX ← (saddrp)
(saddrp) ← AX
AX ← sfrp
sfrp ← AX
AX ← rp
rp ← AX
AX ← (addr16)
(addr16) ← AX
AX ↔ rp
A, CY ← A + byte
(saddr), CY ← (saddr) + byte
A, CY ← A + r
r, CY ← r + A
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, CY ← A + (HL + byte)
A, CY ← A + (HL + B)
A, CY ← A + (HL + C)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
r, CY ← r + A + CY
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + C
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A + (HL + B) + CY
A, CY ← A + (HL + C) + CY
CPU
) selected by the processor clock
Operation
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Flag
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×