UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 151

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(2) Example of setting procedure when using the external subsystem clock
(3) Example of setting procedure when using the subsystem clock as the CPU clock
(4) Example of setting procedure when stopping the subsystem clock
<1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and
Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is
<1> Setting subsystem clock oscillation
<2> Switching the CPU clock (PCC register)
<1> Confirming the CPU clock status (PCC and MCM registers)
<2> Stopping the subsystem clock (OSCCTL register)
Cautions 1. Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the watch
OSCCTL registers)
When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from
port mode to external clock input mode. In this case, input the external clock to the EXCLKS/XT2/P124
pins.
(See 6.6.3 (1) Example of setting procedure when oscillating the XT1 clock and (2) Example of
setting procedure when using the external subsystem clock.)
When CSS is set to 1, the subsystem clock is supplied to the CPU.
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal
high-speed oscillation clock or high-speed system clock.
When OSCSELS is cleared to 0, XT1 oscillation is stopped (the input of the external clock is disabled).
XTSTART
Note The setting of <1> is not necessary when while the subsystem clock is operating.
CSS
CLS
operating.
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.
0
0
0
1
1
timer if it is operating on the subsystem clock.
EXCLKS
PCC2
MCS
0
1
×
1
0
0
0
0
1
Other than above
OSCSELS
Internal high-speed oscillation clock
High-speed system clock
Subsystem clock
PCC1
1
CHAPTER 6 CLOCK GENERATOR
0
0
1
1
0
User’s Manual U17554EJ4V0UD
Note
External clock input
mode
Subsystem Clock Pin
Operation Mode of
PCC0
0
1
0
1
0
f
Setting prohibited
SUB
CPU Clock Status
/2
I/O port
CPU Clock (f
P123/XT1 Pin
CPU
) Selection
External clock input
EXCLKS Pin
P124/XT2/
151