UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 350

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

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1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits)
2. SBF reception error (stop bit is detected with a width of 10.5 bits or less)
Remark R
(i)
INTSR6n
/SBRF6n
SBRT6n
SBF reception
When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is
used for reception. For the reception operation of LIN, see Figure 14-2 LIN Reception Operation.
Reception is enabled when bit 7 (POWER6n) of asynchronous serial interface operation mode register 6n
(ASIM6n) is set to 1 and then bit 5 (RXE6n) of ASIM6n is set to 1. SBF reception is enabled when bit 6
(SBRT6n) of asynchronous serial interface control register 6n (ASICL6n) is set to 1. In the SBF reception
enabled status, the R
reception enable status.
When the start bit has been detected, reception is started, and serial data is sequentially stored in the
receive shift register 6n (RXS6n) at the set baud rate. When the stop bit is received and if the width of SBF
is 11 bits or more, a reception completion interrupt request (INTSR6n) is generated as normal processing. At
this time, the SBRF6n and SBRT6n bits are automatically cleared, and SBF reception ends. Detection of
errors, such as OVE6n, PE6n, and FE6n (bits 0 to 2 of asynchronous serial interface reception error status
register 6n (ASIS6n)) is suppressed, and error detection processing of UART communication is not
performed. In addition, data transfer between receive shift register 6n (RXS6n) and receive buffer register 6n
(RXB6n) is not performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an
interrupt does not occur as error processing after the stop bit has been received, and the SBF reception
mode is restored. In this case, the SBRF6n and SBRT6n bits are not cleared.
R
X
INTSR6n
/SBRF6n
D6n
SBRT6n
SBRT6n: Bit 6 of asynchronous serial interface control register 6n (ASICL6n)
SBRF6n: Bit 7 of ASICL6n
INTSR6n: Reception completion interrupt request
n = 0, 1
R
X
X
D6n
D6n:
“0”
R
1
X
D6n pins (input)
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61
1
X
D6n pins are sampled and the start bit is detected in the same manner as the normal
2
2
3
Figure 14-31. SBF Reception
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User’s Manual U17554EJ4V0UD
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