UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 437

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(a) Read
(b) Write
(a) Read
(b) Write
(11) CAN module interrupt status register (C0INTS)
Interrupt Status Bit
The C0INTS register indicates the interrupt status of the CAN module.
After reset: 0000H
CINTS5
CINTS4
CINTS3
CINTS2
CINTS1
CINTS0
CINTS5-CINTS0
CINTS5-CINTS0
Note The CINTS5 bit is set only when the CAN module is woken up from the CAN sleep mode
Caution Please clear the status bit of this register with software when the confirmation of
C0INTS
C0INTS
Clear
by a CAN bus operation. The CINTS5 bit is not set when the CAN sleep mode has been
released by software.
0
1
0
1
each status is necessary in the interrupt processing, because these bits are not
cleared automatically.
15
15
No related interrupt source event is pending.
A related interrupt source event is pending.
Wakeup interrupt from CAN sleep mode
Arbitration loss interrupt
CAN protocol error interrupt
CAN error status interrupt
Interrupt on completion of reception of valid message frame to message buffer m
Interrupt on normal completion of transmission of message frame from message buffer m
CINTS5 to CINTS0 bits are not changed.
CINTS5 to CINTS0 bits are cleared to 0.
0
7
0
0
7
0
R/W
14
14
0
6
0
0
6
0
CHAPTER 16 CAN CONTROLLER
CINTS5
CINTS5
Address: FF98H, FF99H
Clear
13
13
User’s Manual U17554EJ4V0UD
0
5
0
5
Setting of CINTS5 to CINTS0 Bits
CINTS4
CINTS4
Related Interrupt Source Event
Clear
12
12
0
4
0
4
CAN Interrupt Status Bit
CINTS3
CINTS3
Note
Clear
11
11
0
3
0
3
CINTS2
CINTS2
Clear
10
10
0
2
0
2
CINTS1
CINTS1
Clear
9
0
1
9
0
1
CINTS0
CINTS0
Clear
8
0
0
8
0
0
437