UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 148

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

6.6.2 Example of controlling internal high-speed oscillation clock
148
(1) When restarting oscillation of the internal high-speed oscillation clock
(2) When using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or
(3) When stopping the internal high-speed oscillation clock
(1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clock
(2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and
The following describes examples of clock setting procedures for the following cases.
(b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1
high-speed system clock as peripheral hardware clock
<1> Setting restart of oscillation of the internal high-speed oscillation clock (RCM register)
<2> Waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (RCM
Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the
internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock
<1> • Restarting oscillation of the internal high-speed oscillation clock
<1> Confirming the CPU clock status (PCC and MCM registers)
<2> Stopping the high-speed system clock (MOC register)
Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop
When RSTOP is cleared to 0, the internal high-speed oscillation clock starts operating.
register)
Wait until RSTS is set to 1
• Oscillating the high-speed system clock
2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral
CLS
(See 6.6.2 (1) Example of setting procedure when restarting internal high-speed oscillation
clock).
(This setting is required when using the high-speed system clock as the peripheral hardware clock.
See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of
setting procedure when using the external main system clock.)
0
0
1
Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system
clock.
When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the
CPU clock to the subsystem clock or internal high-speed oscillation clock.
When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled).
internal high-speed oscillation clock is selected as the CPU clock.
hardware clock.
peripheral hardware that is operating on the high-speed system clock.
MCS
0
1
×
Internal high-speed oscillation clock
High-speed system clock
Subsystem clock
Note 2
CHAPTER 6 CLOCK GENERATOR
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User’s Manual U17554EJ4V0UD
Note
CPU Clock Status
Note
Note 1