UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 24

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Note The internal flash memory capacity, internal high-speed RAM capacity, and internal expansion RAM capacity
1.7 Outline of Functions
24
Internal
memory
(bytes)
Memory space
High-speed system clock
(oscillation frequency)
Internal high-speed oscillation
clock (oscillation frequency)
Internal low-speed oscillation
clock (oscillation frequency)
Subsystem clock
(oscillation frequency)
General-purpose registers
Minimum instruction execution
time
Instruction set
I/O ports
Timers
Clock output
Buzzer output
A/D converter
can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size
switching register (IXS).
Flash memory
(self-programming
supported)
Bank
High-speed RAM
Expansion RAM
Timer outputs
Item
Note
Note
Note
Crystal/ceramic oscillation (X
On-chip internal oscillation (8 MHz (TYP.): V
On-chip internal oscillation (240 kHz (TYP.))
Crystal oscillation (XT1), external subsystem clock input (EXCLKS)
(32.768 kHz: V
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
0.1
0.25
operation)
122
• 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
Total:
CMOS I/O
CMOS output
N-ch open-drain I/O
• 16-bit timer/event counter: 4 channels
• 8-bit timer/event counter:
• 8-bit timer:
• Watch timer
• Watchdog timer:
8 (PWM output: 4)
• 78.125 kHz, 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
• 32.768 kHz (subsystem clock: 32.768 kHz)
1.22 kHz, 2.44 kHz, 4.88 kHz, 9.77 kHz (high-speed system clock: 10 MHz)
10-bit resolution × 12 channels
4 to 20 MHz: V
4 to 5 MHz: V
(high-speed system clock: 10 MHz)
μ
μ
μ
μ
s/0.2
PD78F0887
s (subsystem clock: when operating at f
s/0.5
48 K
2 K
−
μ
s/0.4
μ
s/1.0
DD
User’s Manual U17554EJ4V0UD
DD
DD
CHAPTER 1 OUTLINE
= 1.8 to 5.5 V
μ
= 1.8 to 5.5 V)
= 4.0 to 5.5 V, 4 to 10 MHz: V
s/0.8
μ
s/2.0
μ
s/1.6
μ
s/4.0
μ
1
2 channels
2 channels
1 channel
1 channel
PD78F0888
), external main system clock input (EXCLK)
μ
55
50
60 K
μ
s (high-speed system clock: @ f
1
4
2 K
s (TYP.) (internal oscillator clock: @ f
−
64 KB
DD
XT
1 K
= 2.7 to 5.5 V)
= 32.768 kHz)
DD
= 2.7 to 5.5 V,
μ
PD78F0889
96 K
4 K
4
XP
= 20 MHz operation)
RH
= 8 MHz (TYP.)
μ
PD78F0890
128 K
6 K
6
(1/2)