UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 324
UPD78F0890GK(A)-GAJ-AX
Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0890GKA-GAJ-AX.pdf
(732 pages)
Specifications of UPD78F0890GK(A)-GAJ-AX
Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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Address: FF38H After reset: 00H R
Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB61 register.
Symbol
ASIF61
Figure 14-12. Format of Asynchronous Serial Interface Transmission Status Register 61 (ASIF61)
2. To initialize the transmission unit upon completion of continuous transmission, be sure to
TXBF61
TXSF61
Be sure to check that the TXBF61 flag is “0”. If so, write the next transmit data (second byte)
to the TXB61 register. If data is written to the TXB61 register while the TXBF61 flag is “1”, the
transmit data cannot be guaranteed.
check that the TXSF61 flag is “0” after generation of the transmission completion interrupt,
and then execute initialization. If initialization is executed while the TXSF61 flag is “1”, the
transmit data cannot be guaranteed.
7
0
0
1
0
1
If POWER61 = 0 or TXE61 = 0, or if data is transferred to transmit shift register 61 (TXS61)
If data is written to transmit buffer register 61 (TXB61) (if data exists in TXB61)
If POWER61 = 0 or TXE61 = 0, or if the next data is not transferred from transmit buffer register 61
(TXB61) after completion of transfer
If data is transferred from transmit buffer register 61 (TXB61) (if data transmission is in progress)
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61
6
0
5
0
User’s Manual U17554EJ4V0UD
Transmit shift register data flag
4
0
Transmit buffer data flag
3
0
2
0
TXBF61
1
TXSF61
0
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