UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 167

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(1) TI00n pin valid edge selected as capture trigger (CRC0n1 = 1, CRC0n0 = 1)
(2) TI01n pin valid edge selected as capture trigger (CRC0n1 = 0, CRC0n0 = 1)
Cautions 1. Set a value other than 0000H in CR00n in the mode in which clear & start occurs on a match of
Remarks 1. Setting ES0n1, ES0n0 = 1, 0 and ES1n1, ES1n0 = 1, 0 is prohibited.
Falling edge
Rising edge
No capture operation
Falling edge
Rising edge
Both rising and falling edges
3. n = 0 to 3
CR00n Capture Trigger
CR00n Capture Trigger
2. If CR00n is cleared to 0000H in the free-running mode and in the clear mode using the valid edge
3. When P01 or P06 is used as the valid edge input of the TI01n pin, it cannot be used as the timer
4. When CR00n is used as a capture register, read data is undefined if the register read time and
5. Do not rewrite CR00n during TM0n operation.
2. ES0n1, ES0n0:
TM0n and CR00n.
of the TI00n pin, an interrupt request (INTTM00n) is generated when the value of CR00n changes
from 0000H to 0001H following TM0n overflow (FFFFH). In addition, INTTM00n is generated after
a match between TM0n and CR00n, after detecting the valid edge of the TI01n pin, and the timer
is cleared by a one-shot trigger.
output (TO0n). Moreover, when P01 or P06 is used as TO0n, it cannot be used as the valid edge
input of the TI01n pin.
capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
ES1n1, ES1n0:
CRC0n1, CRC0n0: Bits 1 and 0 of capture/compare control register 0n (CRC0n)
Table 7-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03
Bits 5 and 4 of prescaler mode register 0n (PRM0n)
Bits 7 and 6 of prescaler mode register 0n (PRM0n)
Rising edge
Falling edge
Both rising and falling edges
Falling edge
Rising edge
Both rising and falling edges
User’s Manual U17554EJ4V0UD
TI00n Pin Valid Edge
TI01n Pin Valid Edge
ES0n1
ES1n1
0
0
1
0
0
1
ES0n0
ES1n0
1
0
1
0
1
1
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