UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 474

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

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(2) Status in CAN sleep mode
(3) Releasing CAN sleep mode
- Even when initialization mode and sleep mode are not requested simultaneously (i.e the first request has
The CAN module is in one of the following states after it enters the CAN sleep mode.
- The internal operating clock is stopped and the power consumption is minimized.
- The function to detect the falling edge of the CAN reception pin (CRxD) remains in effect to wake up the
- To wake up the CAN module from the CPU, data can be written to PSMODE [1:0] of the CAN module
- The CAN module registers can be read, except for C0LIPT, C0RGPT, C0LOPT, and C0TGPT.
- The CAN message buffer registers cannot be written or read.
- MBON bit of the CAN Global Control register (C0GMCTRL) is cleared.
- A request for transition to the initialization mode is not acknowledged and is ignored.
The CAN sleep mode is released by the following events.
- When the CPU writes 00B to the PSMODE [1:0] bits of the C0CTRL register
- A falling edge at the CAN reception pin (CRxD) (i.e. the CAN bus level shifts from recessive to dominant)
After releasing the sleep mode, the CAN module returns to the operation mode from which the CAN sleep
mode was requested and the PSMODE [1:0] bits of the C0CTRL register are reset to 00B. If the CAN sleep
mode is released by a change in the CAN bus state, the CINTS5 bit of the C0INTS register is set to 1,
regardless of the CIE bit of the C0IE register. After the CAN module is released from the CAN sleep mode, it
participates in the CAN bus again by automatically detecting 11 consecutive recessive-level bits on the CAN
bus. The user application has to wait until MBON = 1, before accessing message buffers again.
When a request for transition to the initialization mode is made while the CAN module is in the CAN sleep
mode, that request is ignored; the CPU has to be released from sleep mode by software first before entering
the initialization mode.
Caution
Caution
Remark m = 0 to 15
not been granted while the second request is made), the request for initialization has priority over the sleep
mode request. The sleep mode request is cancelled when the initialization mode is requested. When a
pending request for initialization mode is present, a subsequent request for Sleep mode request is
cancelled right at the point in time where it was submitted.
CAN module from the CAN bus.
control register (C0CTRL), but nothing can be written to other CAN module registers or bits.
Even if the falling edge belongs to the SOF of a receive message, this message will not be
received and stored. If the CPU has turned off the clock to the CAN while the CAN was in
sleep mode, even subsequently the CAN sleep mode will not be released and PSMODE
[1:0] will continue to be 01B unless the clock to the CAN is supplied again. In addition to
this, the receive message will not be received after that.
Be aware that the release of CAN sleep mode by CAN bus event, and thus the wake up
interrupt may happen at any time, even right after requesting sleep mode, if a CAN bus
event occurs.
CHAPTER 16 CAN CONTROLLER
User’s Manual U17554EJ4V0UD