UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 417

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Caution The actual register address is calculated as follows:
Remarks 1. (R) When read
FAx0H
FAx1H
FAx0H
FAx1H
FAx2H
FAx3H
FAx2H
FAx3H
FAx4H
FAx5H
FAx4H
FAx5H
FAx6H
FAx7H
FAx6H
FAx7H
FAx8H
FAx9H
FAxAH
FAxBH
FAxCH
FAxDH
FAxEH
FAxFH
FAxEH
FAxFH
Address
2. m = 0 to 15
Register Address = Global Register Area Offset (CH dependent) + Offset Address as listed in table
above
(W) When write
C0MDATA01m
C0MDATA0m
C0MDATA1m
C0MDATA23m
C0MDATA2m
C0MDATA3m
C0MDATA45m
C0MDATA4m
C0MDATA5m
C0MDATA67m
C0MDATA6m
C0MDATA7m
C0MDLCm
C0MCONFm
C0MIDLm
C0MIDHm
C0MCTRLm (W)
C0MCTRLm (R)
Symbol
Table 16-19. Bit Configuration of Message Buffer Registers
Message data (byte 0)
Message data (byte 1)
Message data (byte 2)
Message data (byte 2)
Message data (byte 3)
Message data (byte 4)
Message data (byte 4)
Message data (byte 5)
Message data (byte 6)
Message data (byte 6)
Message data (byte 7)
Message data (byte 0)
Message data (byte 1)
Message data (byte 3)
Message data (byte 5)
Message data (byte 7)
Bit 7/15
OWS
ID15
ID23
IDE
ID7
0
0
0
0
0
CHAPTER 16 CAN CONTROLLER
Bit 6/14
RTR
ID14
ID22
ID6
User’s Manual U17554EJ4V0UD
0
0
0
0
0
0
Bit 5/13
MUC
ID13
ID21
MT2
ID5
0
0
0
0
0
Clear MOW Clear IE
Bit 4/12
MOW
MT1
ID12
ID20
ID28
ID4
0
0
0
Bit 3/11
MDLC3
Set IE
ID11
ID19
ID27
MT0
ID3
IE
0
Clear DN Clear TRQ Clear RDY
Bit 2/10
MDLC2
ID10
ID18
ID26
ID2
DN
0
0
0
Set TRQ
MDLC1
Bit 1/9
ID17
ID25
TRQ
ID1
ID9
0
0
Set RDY
MDLC0
Bit 0/8
MA0
ID16
ID24
RDY
ID0
ID8
0
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