SC900841JVKR2 Freescale Semiconductor, SC900841JVKR2 Datasheet - Page 58

• Manufacturer Part Number: SC900841JVKR2
• Description: IC POWER MGT 338-MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of SC900841JVKR2

• Applications: PC's, PDA's
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 338-TBGA
• Input Voltage: 2.8 V to 4.4 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 25. RTC Control Registers Structure and Bit Description
58
Table 24. RTC Date/Time Configuration Register Structure and Bits Description
900841
FUNCTIONAL DEVICE OPERATION
CLOCK GENERATION AND REAL TIME CLOCK (RTC)
HRMODE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MONTH
Name
YEAR
DOW
19/20
DOM
SET
UIP
UIE
AIE
DM
Bits
6:0
2:0
7:3
5:0
7:6
4:0
6:5
7:0
7
0
1
2
3
4
5
6
7
7
Fixed to 010000
This is the Update In Progress (UIP) bit used as a status flag
x0 = Update cycle not in progress
x1 = Update cycle is in progress or will begin soon
Fixed to 0
Hour Format Control
x0 = 12 Hour Mode
x1 = 24 Hour Mode
Data Mode for Time and Calendar Updates
x0 = Binary-Coded-Decimal (BCD)
x1 = Binary
Fixed to 0
Update-Ended Interrupt Enable
x0 = Update-End (UF) bit in Register C is not permitted to assert the interrupt request flag (IRQF) in Register C
x1 = Update-End (UF) bit in Register C is permitted to assert the interrupt request flag (IRQF) in Register C
Alarm Interrupt Enable
x0 = Alarm flag (AF) bit in Register C is not permitted to assert the interrupt request flag (IRQF) in Register C
x1 = Alarm flag (AF) bit in Register C is permitted to assert the interrupt request flag (IRQF) in Register C
Fixed to 0
Set mode enable bit for the program to initialize the time and calendar bytes
x0 = The update cycle functions normally by advancing the counts once-per-second.
x1 = Any update cycle in progress is aborted and the program may initialize the time and calendar bytes without an
update occurring in the midst of initializing.
Day of Week counter register : 1= Sunday ... 7= Saturday
Reserved
Day Of Month Counter Register
Reserved
Months Counter Register
Reserved
THIS BIT IS NOT SUPPORTED
Always Reads 0 (treated as a reserved bit)
Year Counter Register. Note: Values range from 0 to 99
RTCDW (ADDR 0x16 - R/W - Default Value: 0x01)
RTCDM (ADDR 0x17 - R/W - Default Value: 0x01)
RTCM2 (ADDR 0x18 - R/W - Default Value: 0x01)
RTCB (ADDR 0x1B - R/W - Default Value: 0x02)
RTCY (ADDR 0x19 - R/W - Default Value: 0x00)
RTCA (ADDR 0x1A - R - Default Value: 0x20)
Description
Analog Integrated Circuit Device Data
Freescale Semiconductor