SC900841JVKR2 Freescale Semiconductor, SC900841JVKR2 Datasheet - Page 164

• Manufacturer Part Number: SC900841JVKR2
• Description: IC POWER MGT 338-MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of SC900841JVKR2

• Applications: PC's, PDA's
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 338-TBGA
• Input Voltage: 2.8 V to 4.4 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

two registers each with 8 bits of data, CCACCH[7:0]
representing the CC reading high 8-bits, and CCACCL[7:0]
representing the CC reading low 8-bits. The primary coulomb
count that is made available to the host firmware through the
SPI interface, using the above mentioned two registers. A 2s
complement 16-bit value in which a negative sign bit, means
the battery is discharging. A positive sign bit means the
battery is charging, and the magnitude of the value
represents the state of the battery charge, i.e., how much
charge remains. The unmodified coulomb count,
CCOUT[15:0] is also made available through the SPI
interface, and registers RAWCCH and RAWCCL for the 8
high and 8 low bits of the 16-bit data. These two registers
reside in the Freescale dedicated space. These can also be
used for applications that do not require the 2s complement
format.
perform a first order filtering of the signal across RCC. Due to
the sampling of the A to D converter and the filtering applied,
the longer the software waits before retrieving the information
reset to their default values. The ONEC[14:0] will be
programmed to the value of 26 DEC by default. The next step
is to reset the CC by setting the CCCLEAR bit in the
ADCCNTL1 register. The CCCLEAR is automatically cleared
by the PMIC. Finally, the CC will always be running and
counting the battery charge, and recording the reading in the
CCOUT[15:0] register for as long as the CCEN bit in the
ADCCNTL1 register is asserted. Unless the CC has no power
or is in reset, the count will continue.
while CCOUT[15]=0 indicates it is charging. When the CC
count has reached 50% of full value (CCOUT[14] = 1), the
OVERFLOW bit in register ADCINT is set and the PMICINT
pin is asserted, unless the interrupt is masked, in order to
interrupt the system from reading the value of the CC at the
next ADC cycle. The interrupt service routine for the
164
900841
FUNCTIONAL DEVICE OPERATION
ADC SUBSYSTEM
This function will require a 100 nF output capacitor to
At initial power-up, all the digital portions of the CC will be
CCOUT[15]=1 indicates that the battery is discharging,
Charger
Path
From
R
CC
Figure 77. Coulomb Counter Block diagram
100nF
C
CC
ISNSBAT
VBAT
CFM
CFP
from the CC, the higher the accuracy. The capacitor will be
connected between the pins CFP and CFM, see
This counter is preferably reflecting 1 Coulomb per LSB. As
a reminder, 1.0 Coulomb is the equivalent of 1.0 Ampere
during 1.0 second, so a current of 20 mA during 1.0 hour is
equivalent to 72 C. However, since the resolution is much
finer than 1.0 C (LSB of 366.2 µC), the internal counts must
first be rescaled. This can be done by setting the internal
ONEC[14:0] bits. The CCOUT[15:0] counter is then
increased by 1 with every ONEC[14:0] counts of the A to D
converter. ONEC[14:0] = 2731 DEC yields 1C
(2731*366.2 µC) count for CCOUT[15:0] with
RCC=20 mOhm. For the current implementation,
CCOUT[15:0] is desired to have an LSB of 10 mC. To
achieve this, the ONEC register is set internally to 26 DEC
yielding 10 mC count per LSB. The ONEC can be modified
through the SPI in the Freescale dedicated space, using the
ONECLREG and ONECHREG registers
OVERFLOW interrupt will clear the first 15 bits of the
CCADCA register (0-14), and counting will continue. The
CCADCA register is never expected to reach 0x7FFF or
0xFFFF (bits 0-14 being all 1’s). Note that if the battery is
discharging, bit 15 will not be cleared after the OVERFLOW
interrupt.
corrected for offset and gain errors. Digital calibration can be
disabled by setting the CCCALDB bit in register CCREG to 1.
provided in the CCCREG register in the Freescale dedicated
space, so the user has the option to perform all coulomb
counter controls using the coulomb counter registers, instead
of using the GPADC registers. The coulomb counter enable
is a logical OR of CCEN and STARTCC, and the coulomb
counter reset is a logical OR of CCCLEAR and RSTCC. The
user must take note of this to avoid uncertainty of whether the
References
In the existing Freescale IP, the CCOUT counter is 16 bits.
The digital portion of the CC is by default permanently
Redundant control bits STARTCC and RSTCC are also
RESETB
Coulomb
Counter
SPI BITS
RTC
Analog Integrated Circuit Device Data
CCOUT
Freescale Semiconductor
Figure
77.