NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 530

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PDMA Interrupt Status Register (PDMA_ISRx)
Register
PDMA_ISR0
PDMA_ISR1
PDMA_ISR2
PDMA_ISR3
PDMA_ISR4
PDMA_ISR5
PDMA_ISR6
PDMA_ISR7
PDMA_ISR8
Notice: Low Density only support PDMA channel 0.
Bits
[31:2]
[1]
[0]
Note: The PDMA_ISR [TABORT_IF] indicate bus master received ERROR response or not, if bus master received occur it
means that target abort is happened. PDMAC will stop transfer and respond this event to software then go to IDLE state.
When target abort occurred, software must reset PDMA, and then transfer those data again.
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Descriptions
Reserved
BLKD_IF
TABORT_IF
Offset
PDMA_BA_ch0+0x24
PDMA_BA_ch1+0x24
PDMA_BA_ch2+0x24
PDMA_BA_ch3+0x24
PDMA_BA_ch4+0x24
PDMA_BA_ch5+0x24
PDMA_BA_ch6+0x24
PDMA_BA_ch7+0x24
PDMA_BA_ch8+0x24
30
22
14
6
Reserved
Block Transfer Done Interrupt Flag
This bit indicates that PDMA has finished all transfer.
1 = Done
0 = Not finished yet
Software can write 1 to clear this bit to zero
PDMA Read/Write Target Abort Interrupt Flag
1 = Bus ERROR response received
0 = No bus ERROR response received
Software can write 1 to clear this bit to zero
29
21
13
5
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
PDMA Interrupt Status Register CH0
PDMA Interrupt Status Register CH1
PDMA Interrupt Status Register CH2
PDMA Interrupt Status Register CH3
PDMA Interrupt Status Register CH4
PDMA Interrupt Status Register CH5
PDMA Interrupt Status Register CH6
PDMA Interrupt Status Register CH7
PDMA Interrupt Status Register CH8
28
20
12
4
- 530 -
Reserved
Reserved
Reserved
27
19
11
3
Publication Release Date: Dec. 22, 2010
26
18
10
2
BLKD_IF
25
17
9
1
Revision V1.06
Reset Value
0x0X0X_0000
0x0X0X_0000
0x0X0X_0000
0x0X0X_0000
0x0X0X_0000
0x0X0X_0000
0x0X0X_0000
0x0X0X_0000
0x0X0X_0000
TABORT_IF
24
16
8
0