NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 341

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.9
5.9.1
5.9.2
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which
operates in full duplex mode. Devices communicate in master/slave mode with 4-wire bi-direction
interface. The NuMicro™ NUC100 Medium Density contains up to four sets of SPI controller
performing a serial-to-parallel conversion on data received from a peripheral device, and a
parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller
can be set as a master that can drive up to 2 external peripheral slave devices; it also can be
configured as a slave device controlled by an off-chip master device. NuMicro™ NUC100 Low
Density contains two sets of SPI controller only.
This controller supports a variable serial clock for special application and it also supports 2 bit
transfer mode to connect 2 off-chip slave devices at the same time. The SPI controller also
supports PDMA function to access the data buffer.
Serial Peripheral Interface (SPI)
Overview
Features
Up to four sets of SPI controller for NuMicro™ NUC100 Medium Density
Up to two sets of SPI controller for NuMicro™ NUC100 Low Density
Support master or slave mode operation
Support 1-bit or 2-bit transfer mode
Configurable bit length up to 32 bits of a transfer word and configurable word numbers up to
2 of a transaction, so the maximum bit length is 64 bits for each data transfer
Provide burst mode operation, transmit/receive can be transferred up to two times word
transaction in one transfer
Support MSB or LSB first transfer
2 device/slave select lines in master mode, but 1 device/slave select line in slave mode
Support byte reorder in data register
Support byte or word suspend mode
Variable output serial clock frequency in master mode
Support two programmable serial clock frequencies in master mode
Support two channel PDMA request, one for transmitter and another for receiver
NuMicro™ NUC100 Series Technical Reference Manual
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Publication Release Date: Oct 22, 2010
Revision V1.06