NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 185

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupt Control State Register (ICSR)
Register
ICSR
Bits
[31]
[30:29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20:12]
[11:9]
[8:0]
NMIPENDSE
ISRPREEMP
31
23
15
T
T
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
SCS_BA+0xD04
ISRPENDING
Descriptions
NMIPENDSET
Reserved
PENDSVSET
PENDSVCLR
PENDSTSET
PENDSTCLR
Reserved
ISRPREEMPT
ISRPENDING
Reserved
VECTPENDING
Reserved
VECTACTIVE
VECTPENDING[3:0]
30
22
14
6
Reserved
Reserved
R/W
R/W
Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will
activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if
not).
Reserved
Set a pending PendSV interrupt. This is normally used to request a context switch.
Reads back with current state (1 if Pending, 0 if not).
Write 1 to clear a pending PendSV interrupt. This is a write only bit.
Set a pending SysTick. Reads back with current state (1 if Pending, 0 if not).
Write 1 to clear a pending SysTick. This is a write only bit.
Reserved
If set, a pending exception will be serviced on exit from the debug halt state.
This is a read only bit.
Indicates if an external configurable (NVIC generated) interrupt is pending.
This is a read only bit.
Reserved
Indicates the exception number for the highest priority pending exception. The pending
state includes the effect of memory-mapped enable and mask registers. It does not
include the PRIMASK special-purpose register qualifier. A value of zero indicates no
pending exceptions.
This is a read only bit.
Reserved
0 = Thread mode
29
21
13
5
Description
Interrupt Control State Register
PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR
VECTACTIVE[7:0]
28
20
12
4
- 185 -
27
19
11
3
Publication Release Date: Oct 22, 2010
VECTPENDING[8:4]
Reserved
26
18
10
2
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
VECTACTIVE
Reserved
[8]
24
16
8
0