NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 350

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.9.5
In master/slave mode, the active level of device/slave select (SPISSx) signal can be programmed
to low active or high active in SS_LVL bit (SPI_SSR[2]), but the SPISSx0/1 is level trigger or edge
trigger which is defined in SS_LTRIG bit (SPI_SSR[4]). The serial clock (SPICLK) idle state can
be configured as high state or low state by setting the CLKP bit (SPI_CNTRL[11]). It also provides
the bit length of a transaction word in TX_BIT_LEN (SPI_CNTRL[7:3]), the transfer number in
TX_NUM (SPI_CNTRL[8]), and transmit/receive data from MSB or LSB first in LSB bit
(SPI_CNTRL[10]). Users also can select which edge of serial clock to transmit/receive data in
TX_NEG/RX_NEG (SPI_CNTRL[2:1]) registers. Four SPI timing diagrams for master/slave
operations and the related settings are shown as below.
SPICLK
SPISS
Timing Diagram
MOSI
MISO
Master Mode: CNTRL[SLVAE]=0, CNTRL[LSB]=0, CNTRL[TX_NUM]=0x0, CNTRL[TX_BIT_LEN]=0x08
NuMicro™ NUC100 Series Technical Reference Manual
SS_LVL=1
SS_LVL=0
CLKP=0
CLKP=1
1. CNTRL[CLKP]=0, CNTRL[TX_NEG]=1, CNTRL[RX_NEG]=0 or
2. CNTRL[CLKP]=1, CNTRL[TX_NEG]=0, CNTRL[RX_NEG]=1
TX0[7]
RX0[7]
MSB
MSB
Figure 5-58 SPI Timing in Master Mode
RX0[6]
TX0[6]
RX0[5]
TX0[5]
- 350 -
RX0[4]
TX0[4]
Publication Release Date: Dec. 22, 2010
RX0[3]
TX0[3]
RX0[2]
TX0[2]
RX0[1]
TX0[1]
Revision V1.06
RX0[0]
TX0[0]
LSB
LSB