NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 466

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

[5]
[4]
[3]
[2]
[1]
[0]
NuMicro™ NUC100 Series Technical Reference Manual
TXBUSY
RXBUSY
RXPARITY
FRAMERR
PS2DATA
PS2CLK
0 = No overwrite
Write 1 to clear this bit.
Transmit Busy
This bit indicates that the PS2 device is currently sending data.
1 = Currently sending data
0 = Idle
Read only bit.
Receive Busy
This bit indicates that the PS2 device is currently receiving data.
1 = Currently receiving data
0 = Idle
Read only bit.
Received Parity
This bit reflects the parity bit for the last received data byte (odd parity).
Read only bit.
Frame Error
For host to device communication, if STOP bit (logic 1) is not received it is a frame
error. If frame error occurs, DATA line may keep at low state after 12th clock. At this
moment, S/W overrides PS2CLK to send clock till PS2DATA release to high state.
After that, device sends a “Resend” command to host.
1 = Frame error occur
0 = No frame error
Write 1 to clear this bit.
DATA Pin State
This bit reflects the status of the PS2DATA line after synchronizing and sampling.
CLK Pin State
This bit reflects the status of the PS2CLK line after synchronizing.
- 466 -
Publication Release Date: Dec. 22, 2010
Revision V1.06