NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 348

IC MCU 32BIT 32KB FLASH 48LQFP

NUC100LC1BN

Manufacturer Part Number
NUC100LC1BN
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Datasheets

Specifications of NUC100LC1BN

Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Byte Suspend
In master mode, if SPI_CNTRL[19] is set to 1, the hardware will insert a suspend interval 2 ~ 17
serial clock periods between two successive bytes in a transaction word. The byte suspend
setting is the same as the word that using the common bit field of SP_CYCLE register. Note that
when enable the byte suspend function, the setting of TX_BIT_LEN must be programmed as
0x00 only (32 bits per transaction word).
Interrupt
Each SPI controller can generates an individual interrupt when data transfer is finished and the
respective interrupt event flag IF (SPI_CNTRL[16]) will be set. The interrupt event flag will
generates an interrupt to CPU if the interrupt enable bit IE (SPI_CNTRL[17]) is set. The interrupt
event flag IF can be cleared only by writing 1 to it.
REORDER
00
01
10
11
NuMicro™ NUC100 Series Technical Reference Manual
Description
Disable both byte reorder function and byte suspend interval.
Enable byte reorder function and insert a byte suspend internal (2~17 SPICLK) among
each byte. The setting of TX_BIT_LEN must be configured as 0x00 ( 32 bits/ word)
Enable byte reorder function but disable byte suspend function
Disable byte reorder function, but insert a suspend interval (2~17 SPICLK) among each
byte. The setting of TX_BIT_LEN must be configured as 0x00 ( 32 bits/ word)
Table 5-6 Byte Order and Byte Suspend Conditions
Figure 5-56 Timing Waveform for Byte Suspend
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Publication Release Date: Dec. 22, 2010
Revision V1.06

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