NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 371

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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NuMicro™ NUC100 Series Technical Reference Manual
CRST
CACT
CTB
Reserved
TDR_EN
Reserved
PRESCALE
Timer Reset Bit
Set this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to
0.
0 = No effect
1 = Reset Timer’s 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit
Timer Active Status Bit (Read only)
This bit indicates the up-timer status.
0 = Timer is not active
1 = Timer is active
Counter Mode Enable Bit (Low Density only)
This bit is the counter mode enable bit. When Timer is used as an event counter, this
bit should be set to 1 and Timer will work as an event counter triggered by raising edge
of external pin.
1 = Enable counter mode
0 = Disable counter mode
Reserved
Data Load Enable
When TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the
24-bit up-timer value as the timer is counting.
1 = Timer Data Register update enable
0 = Timer Data Register update disable
Reserved
Pre-scale Counter
Clock input is divided by PRESCALE+1 before it is fed to the counter. If PRESCALE =
0, then there is no scaling.
01
10
11
- 371 -
cleared by hardware.
The timer is operating in the periodic mode. The associated interrupt
signal is generated periodically (if IE is enabled).
The timer is operating in the toggle mode. The interrupt signal is
generated periodically (if IE is enabled). And the associated signal (tout)
is changing back and forth with 50% duty cycle. (This mode only
supported in Low Density)
The timer is operating in auto-reload counting mode. The associated
interrupt signal is generated when TDR = TCMPR (if IE is enabled);
however, the 24-bit up-timer counts continuously without reset. (This
mode only supported in Low Density)
Publication Release Date: Oct 22, 2010
Revision V1.06