NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 344

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

NuMicro™ NUC100 Series Technical Reference Manual
Slave Select
In master mode, this SPI controller can drive up to two off-chip slave devices through the slave
select output pins SPISSx0 and SPISSx1. In slave mode, the off-chip master device drives the
slave select signal from the SPISSx0 input port to this SPI controller. In master/slave mode, the
active level of slave select signal can be programmed to low active or high active in SS_LVL bit
(SPI_SSR[2]), and the SS_LTRIG bit (SPI_SSR[4]) defines the slave select signal SPISSx0/1 is
level trigger or edge trigger. The selection of trigger condition depends on what type of peripheral
slave/master device is connected.
In slave mode, if the SS_LTRIG bit is configured as level trigger, the LTRIG_FLAG bit
(SPI_SSR[5]) is used to indicate if both t
he received number and received bits met the requirement
which defines in TX_NUM and TX_BIT_LEN among one transaction done (the transaction done means the
slave select has deactivated.).
Level-trigger / Edge-trigger
In slave mode, the slave select signal can be configured as level-trigger or edge-trigger. In edge-
trigger, the data transfer starts from an active edge and ends on an inactive edge. If master does
not send an inactive edge to slave, the transfer procedure will not be completed and the interrupt
flag of slave will not be set. In level-trigger, the following two conditions will terminate the transfer
procedure and the interrupt flag of slave will be set. The first condition, if master set the slave
select pin to inactive level, it will force slave device to terminate the current transfer no matter how
many bits have been transferred and the interrupt flag will be set. User can read the status of
LTRIG_FLAG bit to check if the data has been completely transferred. The second condition is
that if the number of transferred bits matches the settings of TX_NUM and TX_BIT_LEN, the
interrupt flag of slave will be set.
Automatic Slave Select
In master mode, if the bit AUTOSS (SPI_SSR[3]) is set, the slave select signals will be generated
automatically and output to SPISSx0 and SPISSx1 pins according to SSR[0] (SPI_SSR[0]) and
SSR[1] (SPI_SSR[1]) whether be enabled or not. It means that the slave select signals, which is
enabled in SSR[1:0] register is asserted by the SPI controller when transmit/receive is started by
setting the GO_BUSY bit (SPI_CNTRL[0]) and is de-asserted after the data transfer is finished. If
the AUTOSS bit is cleared, the slave select output signals are asserted and de-asserted by
manual setting and clearing the related bits in SPI_SSR[1:0] register. The active level of the slave
select output signals is specified in SS_LVL bit (SPI_SSR[2]).
Serial Clock
In master mode, set the DIVIDER1 bits (SPI_DIVIDER[15:0]) to program the output frequency of
serial clock to the SPICLK output port. It also supports a variable serial clock if the VARCLK_EN
bit (SPI_CTL[23]) is enabled. In this case, the output frequency of serial clock can be
programmed as one of the two different frequencies which depend on the value of DIVIDER1
(SPI_DIVIDER[15:0]) and DIVIDER2 (SPI_DIVIDER[31:16]). The decision of the variable serial
clock for each cycle is depended on the SPI_VARCLK register.
In slave mode, the off-chip master device drives the serial clock through the SPICLK input port to
this SPI controller.
Publication Release Date: Dec. 22, 2010
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Revision V1.06