NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 476
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/28/73/287342/nuc100lc1bn_sml.jpg)
NUC100LC1BN
Manufacturer Part Number
NUC100LC1BN
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC100LC1BN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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I
Register
I2S_CLKDIV I2S_BA+0x04
Bits
[31:16]
[15:8]
[7:3]
[2:0]
2
S Clock Divider (I2S_CLKDIV)
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
Descriptions
Reserved
BCLK_DIV [7:0]
Reserved
MCLK_DIV[2:0]
30
22
14
6
Reserved
R/W
R/W
Reserved
Bit Clock Divider
If I
Software can program these bits to generate sampling rate clock frequency.
F_BCLK = F_I2SCLK /(2x(BCLK_DIV + 1))
Reserved
Master Clock Divider
If chip external crystal frequency is (2xMCLK_DIV)*256fs then software can program
these bits to generate 256fs clock frequency to audio codec chip. If MCLK_DIV is set to
0, MCLK is the same as external clock input.
For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz,
set MCLK_DIV=1.
F_MCLK = F_I2SCLK/(2x(MCLK_DIV)) (When MCLK_DIV is >= 1 )
F_MCLK = F_I2SCLK (When MCLK_DIV is set to 0 )
29
21
13
5
2
S operates in master mode, bit clock is provided by NuMicro™ NUC100 series.
Description
I
2
S Clock Divider Control Register
28
20
12
BCLK_DIV [7:0]
4
- 476 -
Reserved
Reserved
27
19
11
3
Publication Release Date: Dec. 22, 2010
26
18
10
2
MCLK_DIV[2:0]
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
24
16
8
0
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