NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 354

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Example 2, SPI controller is set as a slave device that controlled by an off-chip master device,
and supposes the off-chip master device to access the on-chip SPI slave controller through the
SPI interface with the following specifications:
Basically, the specification of the connected off-chip master device should be referred in details
before the following steps:
1.
2.
3.
4.
5.
6.
7.
8.
Data bit is latched on positive edge of serial clock
Data bit is driven on negative edge of serial clock
Data is transferred from LSB first
SPICLK is idle at high state
Only one byte of data to be transmitted/received in a transaction
Slave select signal is high level trigger
Select high level and level trigger for the input of slave select signal in the Slave Select
Active Level bit SS_LVL (SPI_SSR[2] = 1) and the Slave Select Level Trigger bit
SS_LTRIG (SPI_SSR[4] = 1).
Write the related settings into the SPI_CNTRL register to control this SPI slave actions, set
this SPI controller as slave device in SLAVE bit (SPI_CNTRL[18] = 1), select the serial
clock idle state at high in CLKP bit (SPI_CNTRL[11] = 1), select data transmitted at
negative edge of serial clock in TX_NEG bit (SPI_CNTRL[2] = 1), select data latched at
positive edge of serial clock in RX_NEG bit (SPI_CNTRL[1] = 0), set the bit length of word
transfer as 8 bits in TX_BIT_LEN bit field (SPI_CNTRL[7:3] = 0x08), set only one time of
word transaction in TX_NUM (SPI_CNTRL[9:8] = 0x0), set LSB transfer first in LSB bit
(SPI_CNTRL[10] = 1), and don’t care the SP_CYCLE bit field (SPI_CNTRL[15:12]) due to
not burst mode in this case.
If this SPI slave will transmits (be read) one byte data to the off-chip master device, write
the byte data that will be transmitted into the TX0[7:0] (SPI_TX0[7:0]) register.
If this SPI slave just only receives (be written) one byte data from the off-chip master
device, you don’t care what data will be transmitted and just write 0xFF into the
SPI_TX0[7:0] register.
Enable the GO_BUSY bit (SPI_CNTRL[0] = 1) to wait for the slave select trigger input and
serial clock input from the off-chip master device to start the data transfer at the SPI
interface.
Waiting for SPI interrupt occurred (if the Interrupt Enable IE bit is set) or just polling the
GO_BUSY bit till it be cleared to 0 by hardware automatically.
Read out the received one byte data from RX[7:0] (SPI_RX0[7:0]) register.
Go to 3) to continue another data transfer or disable the GO_BUSY bit to stop data transfer.
NuMicro™ NUC100 Series Technical Reference Manual
- 354 -
Publication Release Date: Dec. 22, 2010
Revision V1.06