NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 360

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SPI Slave Select Register (SPI_SSR)
Register
SPI_SSR
Bits
[31:6]
[5]
[4]
[3]
[2]
[1:0]
31
23
15
7
Reserved
NuMicro™ NUC100 Series Technical Reference Manual
Offset
SPI0_BA+0x08
Descriptions
Reserved
LTRIG_FLAG
SS_LTRIG
AUTOSS
SS_LVL
SSR
30
22
14
6
LTRIG_FLAG
R/W
R/W
Reserved
Level Trigger Flag
When the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the
received bit number is met the requirement or not.
1 = The transaction number and the transferred bit length met the specified
0 = The transaction number or the transferred bit length of one transaction doesn't
Note: This bit is READ only
Slave Select Level Trigger (Slave only)
1 = The slave select signal will be level-trigger. It depends on SS_LVL to decide the
0 = The input slave select signal is edge-trigger. This is the default value.
Automatic Slave Select (Master only)
1 = If this bit is set, SPISSx0/1 signals are generated automatically. It means that
0 = If this bit is cleared, slave select signals are asserted and de-asserted by setting
Slave Select Active Level
It defines the active level of slave select signal (SPISSx0/1).
1 = The slave select signal SPISSx0/1 is active at high-level/rising-edge.
0 = The slave select signal SPISSx0/1 is active at low-level/falling-edge.
Slave Select Register (Master only)
If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper
SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
29
21
13
5
requirements which defined in TX_NUM and TX_BIT_LEN.
meet the specified requirements.
signal is active low or active high.
device/slave select signal, which is set in SSR[1:0] register is asserted by the SPI
controller when transmit/receive is started by setting GO_BUSY, and is de-
asserted after each transmit/receive is finished.
and clearing related bits in SSR[1:0] register.
Description
Slave Select Register
SS_LTRIG
28
20
12
4
- 360 -
Reserved
Reserved
Reserved
AUTOSS
27
19
11
3
Publication Release Date: Dec. 22, 2010
SS_LVL
26
18
10
2
25
17
9
1
Revision V1.06
SSR
Reset Value
0x0000_0000
24
16
8
0