NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 215

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.4
5.4.1
5.4.2
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
compliant with USB 2.0 full-speed device specification and support control/bulk/interrupt/
isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE.
Users need to set the effective starting address of SRAM for each endpoint buffer through “buffer
segmentation register (BUFSEGx)”.
This device controller contains 6 configurable endpoints. Each endpoint can be configured as IN,
OUT, or SETUP packet type. The function address of the device and endpoint number in each
endpoint shall be configured properly in advance for receive or transmit a data packet. The
transmit/receive length in each endpoint is defined in maximum payload register (MXPLDx) and
the handshakes between Host and Device are handled in it.
There are four different interrupt events in this controller. They are the wake up function, device
plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend
and resume, etc. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of interrupt
occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disable function is also support for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables DRVSE0 bit (USB_DRVSE0), the USB
controller will force the output of USB_DP and USB_DM to level low and its function is disabled.
After disable the DRVSE0 bit, host will enumerate the USB device again.
Reference: Universal Serial Bus Specification Revision 1.1
This Universal Serial Bus (USB) performs a serial interface with a single connector type for
attaching all USB peripherals to the host system. Following is the feature listing of this USB.
USB Device Controller (USB)
Overview
Features
NuMicro™ NUC100 Series Technical Reference Manual
Compliant with USB 2.0 Full-Speed specification
Provide 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB
and BUS)
Support Control/Bulk/Interrupt/Isochronous transfer type
Support suspend function when no bus activity existing for 3 ms
Provide 6 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
and maximum 512 bytes buffer size
Provide remote wakeup capability
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Publication Release Date: Oct 22, 2010
Revision V1.06