NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 400

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Line Control Register (UA_LCR)
Register
UA_LCR
Bits
[31:7]
[6]
[5]
[4]
[3]
[2]
Reserved
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Descriptions
Reserved
BCB
SPE
EPE
PBE
NSB
Offset
UART0_BA+0x0C R/W
UART1_BA+0x0C R/W
UART2_BA+0x0C R/W
BCB
30
22
14
6
Reserved
Break Control Bit
When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State
(logic 0). This bit acts only on TX and has no effect on the transmitter logic.
Stick Parity Enable
1 = When bits PBE , EPE and SPE are set, the parity bit is transmitted and checked as
0 = Disable stick parity
Even Parity Enable
1 = Even number of logic 1’s are transmitted or checked in the data word and parity
0 = Odd number of logic 1’s are transmitted or checked in the data word and parity bits.
This bit has effect only when bit 3 (parity bit enable) is set.
Parity Bit Enable
1 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of
0 = Parity bit is not generated (transmit data) or checked (receive data) during transfer.
Number of “STOP bit”
1= One and a half “ STOP bit” is generated in the transmitted data when 5-bit word
0= One “ STOP bit” is generated in the transmitted data
Two “STOP bit” is generated when 6-, 7- and 8-bit word length is selected.
SPE
29
21
13
R/W
5
cleared. When PBE and SPE are set and EPE is cleared, the parity bit is
transmitted and checked as set.
bits.
the serial data.
length is selected;
UART0 Line Control Register
UART1 Line Control Register
UART2 Line Control Register
Description
EPE
28
20
12
4
- 400 -
Reserved
Reserved
Reserved
PBE
27
19
11
3
Publication Release Date: Dec. 22, 2010
NSB
26
18
10
2
25
17
9
1
Revision V1.06
WLS
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
24
16
8
0