MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 96

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

ColdFire Core
2.8.2
Table 2-21
2-28
Address Error Caused by an attempted execution transferring control to an odd instruction address (that is, if bit 0 of the target
Access Error
Exception
•
Vector number—This 8-bit field, vector[7–0], defines the exception type. It is calculated by the
processor for internal faults and is supplied by the peripheral for interrupts. See
describes MCF5272 exceptions.
Processor Exceptions
Caused by an error when accessing memory. For an access error on an instruction fetch, the processor
postpones the error reporting until the instruction at the faulted reference is executed. Thus, faults that occur
during instruction prefetches that are followed by a change of instruction flow do not generate an exception.
When the processor attempts to execute an instruction with a faulted opword or extension word, the access
error is signaled, and the instruction is aborted. For this type of exception, the programming model is not
altered by the faulted instruction.
If an access error occurs on an operand read, the processor immediately aborts the current instruction
execution and initiates exception processing. In this case, any address register changes caused by the
auto-addressing modes, (An)+ and -(An), have already occurred. In addition, if an access error occurs during
the execution of a MOVEM instruction loading from memory, registers updated before the fault occurs contain
the memory operand.
Due to the processor pipeline implementation, a write cycle may be decoupled from the execution of the
instruction causing the write. Thus, if an access error occurs on an operand write, the signaling of the error is
imprecise. Accordingly, the PC contained in the exception stack frame represents the location in the program
when the access error is signaled, not necessarily the instruction causing the fault. All programming model
updates associated with the write instruction are complete. The NOP instruction can be used to help identify
write access errors. A NOP is not executed until all previous operations, including any pending writes are
complete. Thus if any previous write terminates with an access error, it is guaranteed to be reported on the
NOP.
address is set), an attempted use of a word-sized index register (Xi.w) or a scale factor of 8 on an indexed
effective addressing mode, or attempted execution of an instruction with a full-format indexed addressing
mode.
0101–011x
1101–111x
0000-001x
FS[3–0]
0100
1000
1001
101x
1100
MCF5272 ColdFire
Reserved
Error on instruction fetch
Reserved
Error on operand write
Attempted write to write-protected space
Reserved
Error on operand read
Reserved
Table 2-20. Fault Status Encodings
Table 2-21. MCF5272 Exceptions
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
Definition
Freescale Semiconductor
Table
2-18.