MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 492

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
23.3.3
Table 23-8
1
2
23-8
B6a
B6b
B6c
B6d
B6e
B7a
B7b
B7c
B8
B9
B11
B12
B13
All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0.
Data output is held valid for one CPU clock period after deassertion of BS[3:0]
Name
2
SDCLK to chip selects (CS[6:0]) valid
SDCLK to byte enables (BS[3:0]) valid
SDCLK to output enable (OE) valid
SDCLK to write enable (R/W) valid
SDCLK to reset output (RSTO) valid
SDCLK to control output (CS[6:0], OE) invalid (output hold)
SDCLK to control output (BS[3:0], R/W) invalid (output hold)
SDCLK to reset output (RSTO) invalid (output hold)
SDCLK to address (A[22:0]) valid
SDCLK to address (A[22:0]) invalid (output hold)
SDCLK to data output (D[31:0]) valid
SDCLK to data output (D[31:0]) invalid (output hold)
SDCLK to data output (D[31:0]) high impedance
lists processor bus output timings.
Processor Bus Output Timing Specifications
Above 48 MHz, the memory bus may need to be configured for one wait
state. It is the responsibility of the user to determine the actual frequency at
which to insert a wait state since this depends on the access time of SRAM
or SDRAM used in a particular system implementation.
Wait states are inserted for SRAM accesses by programming bits 6–2 of the
chip select option registers.
A wait state is added for SDRAM read accesses by setting bit 4 of the
SDRAM control register.
MCF5272 ColdFire
Table 23-8. Processor Bus Output Timing Specifications
Characteristic
®
Address and Attribute Outputs
Integrated Microprocessor User’s Manual, Rev. 3
Control Outputs
Data Outputs
NOTE
1
Min
1.5
1.0
1.5
—
—
—
—
—
—
—
—
4
1
0–66 MHz
Freescale Semiconductor
Max
13.5
13.0
9.5
9.0
12
11
—
—
—
—
—
8
6
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS