MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 243

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

11.5.15 Transmit Control Register (TCR)
The TCR register,
Table 11-22
Freescale Semiconductor
31–3
Bits
2
1
0
Reset
Reset
Field
Field
Addr
R/W
R/W
Name
FDEN
31
15
HBC
GTS
describes the TCR fields.
—
Figure
Reserved, should be cleared.
Full duplex enable. If set, frames are transmitted independent of carrier sense and collision inputs. This
bit should only be modified when ETHER_EN is deasserted.
Heartbeat control. If set, the heartbeat check is performed following end of transmission and the HB
bit in the status register is set if the collision input does not assert within the heartbeat window. This bit
should be modified only when ETHER_EN is deasserted.
Graceful transmit stop. When this bit is set, the MAC stops transmission after any current frame is
complete and the GRA interrupt in the INTR_EVENT register is asserted. If frame transmission is not
currently underway, the GRA interrupt is asserted immediately. Once transmission is complete, a
restart is accomplished by clearing the GTS bit. The next frame in the transmit FIFO is then transmitted.
If an early collision occurs during transmission when GTS = 1, transmission stops after the collision.
The frame is transmitted again once GTS is cleared. Note that there may be old frames in the transmit
FIFO that are transmitted when GTS is reasserted. To avoid this, deassert ETHER_EN following the
GRA interrupt.
MCF5272 ColdFire
11-19, controls the operational mode of the transmit block
Figure 11-19. Transmit Control Register (TCR)
Table 11-22. TCR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
—
0000_0000_0000_0000
0000_0000_0000_0000
MBAR + 0x984
Read/Write
Read/Write
—
Description
3
FDEN HBC GTS
2
Ethernet Module
1
16
0
11-25