MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 498

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
23.5
Table 23-10
1
Figure 23-9
23-14
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SD16
Name
All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0.
SDRAM Interface Timing Specifications
SDCLK to address output A[22:0] valid
SDCLK to address output A[22:0] invalid (output hold)
SDCLK to DQM[3:0] valid
SDCLK to DQM[3:0] invalid (output hold)
SDCLK to data output (D[31:0]) valid (signal from driven or three-state)
SDCLK to data output (D[31:0]) invalid (output hold)
SDCLK to CAS0, RAS0, SDBA[1:0], SDCLKE, SDRAMWE, valid
SDCLK to CAS0, RAS0, SDBA[1:0], SDCLKE, SDRAMWE, invalid (output hold)
SDCLK to SDCS valid
SDCLK to SDCS invalid (output hold)
SDCLK to A10_PRECHG valid
SDCLK to A10_PRECHG invalid (output hold)
SDCLK to data output (D[31:0]) high impedance
Data input (D[31:0]) valid to SDCLK (setup) (pipeline mode, SDRAM control register b4
= 1)
Data input (D[31:0]) valid to SDCLK (setup) (straight-through mode, SDRAM control
register b4 = 0)
SDCLK to data input (D[31:0]) invalid (hold)
shows SDRAM timings listed in
lists SDRAM interface timings.
Above 48 MHz, the memory bus may need to be configured for one wait
state. It is the responsibility of the user to determine the actual frequency at
which to insert a wait state since this depends on the access time of SRAM
or SDRAM used in a particular system implementation.
Wait states are inserted for SRAM accesses by programming bits 6–2 of the
chip select option registers.
A wait state is added for SDRAM read accesses by setting bit 4 of the
SDRAM control register.
MCF5272 ColdFire
Table 23-10. SDRAM Interface Timing Specifications
®
Characteristic
Integrated Microprocessor User’s Manual, Rev. 3
Table
Control Inputs
NOTE
23-10.
1
Freescale Semiconductor
13.0
Min
1.0
1.0
1.0
5.5
—
—
—
—
—
—
—
0–66 MHz
1
1
1
0
13.0
Max
13.0
9.5
—
—
—
—
—
—
—
—
—
9
7
8
6
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS