MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 131

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

5.4.6
The PC breakpoint register (PBR) defines an instruction address for use as part of the trigger. This
register’s contents are compared with the processor’s program counter register when TDR is configured
appropriately. PBR bits are masked by setting corresponding PBMR bits. Results are compared with the
processor’s program counter register, as defined in TDR.
Table 5-12
Figure 5-9
Table 5-13
Freescale Semiconductor
31–0
31–0
Bits
Bits
DRc[4–0]
DRc[4–0]
Reset
Address
Field
Name
R/W Write. PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through
Reset
Mask
Name
Field
R/W
shows PBMR.
describes PBR fields.
describes PBMR fields.
Program Counter Breakpoint/Mask Registers
the BDM port using the
Set
(PBR, PBMR)
31
PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to the
appropriate PC bit. Set PBMR bits cause PBR bits to be ignored.
31
Descriptions.”
PC breakpoint address. The 32-bit address to be compared with the PC as a breakpoint trigger.
Write. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG
Figure 5-10. Program Counter Breakpoint Mask Register (PBMR)
MCF5272 ColdFire
Figure 5-9. Program Counter Breakpoint Register (PBR)
instruction and via the BDM port using the wdmreg command.
RDMREG
Table 5-13. PBMR Field Descriptions
Table 5-12. PBR Field Descriptions
®
and
Integrated Microprocessor User’s Manual, Rev. 3
WDMREG
Program Counter
commands using values shown in
Description
0x08
Mask
0x09
Description
—
—
Figure 5-9
shows the PC breakpoint register.
Section 5.5.3.3, “Command
Debug Support
0
0
5-13