MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 316

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Physical Layer Interface Controller (PLIC)
13.5.8
All bits in this register are cleared on hardware or software reset.
The PLCR is an 8-bit register containing the configuration information for all four ports on the MCF5272.
13.5.9
All bits in these registers are read/write and are cleared on hardware or software reset.
The PnICR registers contain interrupt configuration bits for each of the four ports on the MCF5272.
13-20
Bits
7-6
5-4
3-2
1-0
PLCIR0–3 IE
Reset
Addr
R/W
Loopback Control Register (PLCR)
Interrupt Configuration Registers (P0ICR–P3ICR)
Name
LM3
LM2
LM1
LM0
15
In loopback mode, the respective port must be enabled (using
PnCR[ON/OFF]) along with the B1 and B2 channels (using PnCR[ENB1,
ENB2]) and the D channel (using PDRQR[DCNTI] when in IDL mode, for
instance). Also, if more than one of ports 1, 2, or 3 are programmed in
loopback mode, it is necessary to program the appropriate frame sync
function using the sync delay registers discussed in
Delay Registers
Reset
14
Field
Addr
R/W
Figure 13-21. Interrupt Configuration Registers (P0ICR–P3ICR)
Loopback mode control, port 3.
00 Normal
01 Auto-echo
10 Local Loopback
11 Remote Loopback
Loopback mode control, port 2. See LM3.
Loopback mode control, port 1. See LM3.
Loopback mode control, port 0. See LM3.
MCF5272 ColdFire
MBAR + 0x0358 (P0ICR); 0x035A (P1ICR); 0x035C (P2ICR); 0x035E (P3ICR)
—
7
Figure 13-20. Loopback Control Register (PLCR)
LM3
12
(P0SDR–P3SDR).”
Table 13-3. PLCR Field Description
GCR GCT GMR GMT
6
11
®
Integrated Microprocessor User’s Manual, Rev. 3
10
5
LM2
9
0000_0000_0000_0000
NOTE
MBAR + 0x38F
0000_0000
Read/Write
4
Read/Write
8
Description
7
3
—
LM1
6
DTIE B2TIE B1TIE DRIE B2RIE B1RIE
Section 13.5.21, “Sync
2
5
4
1
LM0
3
0
Freescale Semiconductor
2
1
0