MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 87

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

2.7
The timing data presented in this section assumes the following:
Freescale Semiconductor
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The OEP is loaded with the opword and all required extension words at the beginning of each
instruction execution. This implies that the OEP spends no time waiting for the IFP to supply
opwords and/or extension words.
The OEP experiences no sequence-related pipeline stalls. For the MCF5272,the most common
example of this type of stall involves consecutive store operations, excluding the MOVEM
instruction. For all store operations (except MOVEM), certain hardware resources within the
processor are marked as busy for two clock cycles after the final DSOC cycle of the store
instruction. If a subsequent store instruction is encountered within this two-cycle window, it is
stalled until the resource again becomes available. Thus, the maximum pipeline stall involving
consecutive store operations is two cycles.
The OEP can complete all memory accesses without memory causing any stall conditions. Thus,
timing details in this section assume an infinite zero-wait state memory attached to the core.
All operand data accesses are assumed to be aligned on the same byte boundary as the operand size:
— 16-bit operands aligned on 0-modulo-2 addresses
— 32-bit operands aligned on 0-modulo-4 addresses
Operands that do not meet these guidelines are misaligned.
decomposes a misaligned operand reference into a series of aligned accesses.
1
Instruction Timing
Each timing entry is presented as C(r/w), described as follows:
C is the number of processor clock cycles, including all applicable operand fetches and writes, as
well as all internal core cycles required to complete the instruction execution.
r/w is the number of operand reads (r) and writes (w) required by the instruction. An operation
performing a read-modify write function is denoted as (1/1).
A[1:0]
10
x1
x1
MCF5272 ColdFire
Table 2-9. Misaligned Operand References
Word
Long
Long
Size
®
Integrated Microprocessor User’s Manual, Rev. 3
Byte, Byte
Byte, Word, Byte
Word, Word
Bus Operations
Table 2-9
2(1/0) if read
1(0/1) if write
3(2/0) if read
2(0/2) if write
2(1/0) if read
1(0/1) if write
Additional C(R/W)
shows how the core
1
ColdFire Core
2-19