MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 509

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Figure 23-18
Table 23-19
Freescale Semiconductor
Name
P30
P31
P32
P33
P34
P35
P38
P39
P40
P41
P42
FSC input high before the falling edge of DCL0, DCL1 (setup time)
FSC0 input low before the rising edge of DCL0 (deassertion setup time),
FSC1 input low before the rising edge of DCL1 (deassertion setup time)
FSC0 input high after the falling edge of DCL0 (hold time),
FSC1 input high after the falling edge of DCL1 (hold time)
DCL0, DCL1 clock frequency
DCL0, DCL1 pulse-width low
DCL0, DCL1 pulse-width high
Delay from rising edge of FSC0 to low-z and valid data on DOUT0
Delay from rising edge of FSC1 to low-z and valid data on DOUT1
Delay from rising edge of DFSC2 to low-z and valid data on DOUT1
Delay from rising edge of DFSC3 to low-z and valid data on DOUT1, DOUT3
Delay from rising edge of DCL0 to data valid on DOUT0,
Delay from rising edge of DCL1 to data valid on DOUT1, DOUT3
Delay from rising edge of DCL0 to high-z on DOUT0,
Delay from rising edge of DCL1 to high-Z on DOUT1, DOUT3
Data valid on DIN0 before rising edge of DCL0,
Data valid on DIN1 or DIN3 before rising edge of DCL1
Data valid on DIN0 after rising edge of DCL0,
Data valid on DIN1 or DIN3 after rising edge of DCL1
DOUT[0,1,3]
DFSC[2:3]
FSR[0,1]
DCL[0:1]
DIN[0:3]
lists timings for GCI slave mode.
shows IDL slave timings listed in
P15
MCF5272 ColdFire
Table 23-19. GCI Slave Mode Timing, PLIC Ports 0–3
P16
P17
P20
Characteristic
Figure 23-18. IDL Slave Timing
®
Integrated Microprocessor User’s Manual, Rev. 3
P25
P21
Table
P26
23-18.
P14
P18
P23
P14
P19
P24
P22
Min
25
25
25
45
45
25
25
—
—
—
—
8192
Max
55
55
30
30
30
—
—
—
—
Electrical Characteristics
% of DCL period
% of DCL period
Unit
KHz
nS
nS
nS
nS
nS
nS
nS
nS
23-25