MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 238

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Ethernet Module
11.5.10 FIFO Receive Start Register (FRSR)
The FRSR register,
FIFO. FRSR marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses
addresses from TFSR to FRSR - 4. The receive FIFO uses addresses from FRSR to FRBR - 4. The value
in this register must be added to MBAR + 0x800 to determine the absolute address.
FRSR needs to be written only to change the default value.
Table 11-17
11-20
31–11
Bits
9–2
1–0
10
Reset
Reset
Field
Field
Addr
R/W
R/W
R_FSTART
describes the FRSR fields.
Name
—
—
1
31
15
Figure
MCF5272 ColdFire
0000_0
Reserved, should be cleared.
Reserved, should be set.
Receive FIFO starting address. Address of first receive FIFO location. Acts as delimiter between
receive and transmit FIFOs.
Reserved, should be cleared.
—
11-14, is programmed by the user to indicate the starting address of the receive
Figure 11-14. FIFO Receive Start Register (FRSR)
11
Table 11-17. FRSR Field Descriptions
10
1
1
®
Integrated Microprocessor User’s Manual, Rev. 3
9
0000_0000_0000_0000
MBAR + 0x8D0
Read/Write
Read/Write
—
01_0000_00
R_FSTART
Description
2
Freescale Semiconductor
1
00
—
16
0