MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 203

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

As
be refined by setting SDCR[INV], which inverts the SDRAM clock. SDCR[REG] must always be cleared
when SDCR[INV] is set.
The incoming data setup time should be inspected during reads. The active clock edge event of SDCLK
now precedes the MCF5272 internal active clock edge event when (REG = 0). This behavior is frequency
dependent. The two following scenarios are possible:
If the delay between shifted SDCLK and following internal system clock edge is shorter than the read
access time of the SDRAM, data is sampled with the true CAS latency.
Freescale Semiconductor
.
Figure 9-6
•
•
Internal
High-speed timing refinement with true CAS latency. See
Low-speed timing refinement with reduced effective CAS latency.
Internal CLK
SDCLK
Data bus
SDCLK
Data
CLK
shows timing relationships between SDCLK and the remaining data and control signals can
If the delay difference between the fastest data signal and the slowest control
signal exceeds half of the clock cycle time, the clock shift can cause
hold-time violations on control signals.
Figure 9-7. Timing Refinement with True CAS Latency and Inverted SDCLK
MCF5272 ColdFire
Figure 9-6. Timing Refinement with Inverted SDCLK
®
Integrated Microprocessor User’s Manual, Rev. 3
Data setup delay
NOTE
Shifted delay of SDCLK
CASL = 2
T
SDCLK_to_CLK
Shifted delay of SDCLK
- T
Figure
acc
< 0 => true CAS latency
Delay SDCLK to CLK
9-7.
SDRAM read access time
SDRAM Controller
9-13