MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 168

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM)
6-8
30–27
15-11
Bits
31
26
25
24
23
22
21
20
19
18
17
16
TIMERPDN Timer power-down enable. Controls the clocking to the timer module.
UART1PDN UART1 power-down enable. Controls the clocking to the UART1 module. Clocking to the UART1
UART0PDN UART0 power-down enable. Controls the clocking to the UART0 module. Clocking to the UART0
DRAMPDN
ENETPDN
PWMPDN
GPIOPDN
QSPIPDN
BDMPDN
DMAPDN
USBPDN
PLIPDN
Field
—
—
Debug power-down enable. Controls the clocking to the debug module.
0 Clock enabled.
1 Clock disabled.
Reserved, should be cleared.
Ethernet power-down enable. Controls the clocking to the ethernet module.
0 Clock enabled.
1 Clock disabled.
PLIC power-down enable. Controls the clocking to the PLIC module.
0 Clock enabled.
1 Clock disabled.
DRAM controller power-down enable. Controls the clocking to the DRAM controller module.
0 Clock enabled.
1 Clock disabled.
DMA controller power-down enable. Controls the clocking to the DMA controller module.
0 Clock enabled.
1 Clock disabled.
PWM power-down enable. Controls the clocking to the PWM module.
0 Clock enabled.
1 Clock disabled.
QSPI power-down enable. Controls the clocking to the QSPI module.
0 Clock enabled.
1 Clock disabled.
0 Clock enabled.
1 Clock disabled.
Parallel port power-down enable. Controls the clocking to the parallel port module.
0 Clock enabled.
1 Clock disabled.
USB power-down enable. Controls the clocking to the USB module. Clocking to the USB module may
be turned on by USD_D+ or INT1/USB_WOR, at which time this bit is automatically cleared.
0 Clock enabled.
1 Clock disabled.
module may be restored when a change in signal level is detected on UART1RxD, at which time this
bit is automatically cleared.
0 Clock enabled.
1 Clock disabled.
module may be restored when a change in signal level is detected on UART0RxD, at which time this
bit is automatically cleared.
0 Clock enabled.
1 Clock disabled.
Reserved, should be cleared.
MCF5272 ColdFire
Table 6-5. PMR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
Freescale Semiconductor