MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 255

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

11.6.1.2
Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s TxBDs.
The FEC confirms transmission or indicates error conditions using the BDs to inform the host that the
buffers have been serviced. In the TxBD, the user initializes the R, W, L, and TC bits and the length (in
bytes) in the first word and the buffer pointer in the second words.
If L = 0, then the FEC sets the R bit to 0 in the first word of the BD when the buffer is sent as a DMA.
Status bits are not modified.
If L = 1, then the FEC sets the R bit to 0 and will modify the DEF, HB, LC, RL, RC, UN, and CSL status
bits in the first word of the BD after the buffer is sent as a DMA, and frame transmission is complete.
The TxBD fields are detailed in
Freescale Semiconductor
Bits
15
14
13
12
11
10
9
+0
+2
+4
+6
15
R
Ethernet Transmit Buffer Descriptor
Name
DEF
TO1
TO2
TC
W
R
L
TO1
14
MCF5272 ColdFire
W
13
Ready. Written by the FEC (= 0) and user (= 1).
0 The data buffer associated with this BD is not ready for transmission. The user is free to
1 The data buffer, which has been prepared for transmission by the user, has not been
Transmit software ownership bit.Reserved for use by software. This read/write bit is not modified
by hardware, nor does its value affect hardware.
Wrap. Written by the user.
0 The next buffer descriptor is found in the consecutive location.
1 The next buffer descriptor is found at the location defined in ETDSR.
Transmit software ownership bit. Reserved for use by software. This read/write bit is not modified
by hardware, nor does its value affect hardware.
Last in frame. Written by the user.
0 The buffer is not the last in the transmit frame.
1 The buffer is the last in the transmit frame.
Tx CRC. Written by the user and is only valid if L = 1.
0 End transmission immediately after the last data byte.
1 Transmit the CRC sequence after the last data byte.
Defer indication. Written by the FEC and is only valid if L = 1. The FEC had to defer while trying
to transmit a frame. This bit is not set if a collision occurs during transmission.
manipulate this BD or its associated data buffer. The FEC clears this bit after the buffer has
been transmitted or after an error condition is encountered.
transmitted or is currently being transmitted. No fields of this BD may be written by the user
once this bit is set.
TO2
Figure 11-28. Transmit Buffer Descriptor (TxBD)
12
Table
Table 11-35. TxBD Field Descriptions
11
L
®
11-35.
TC
Integrated Microprocessor User’s Manual, Rev. 3
10
Tx Data Buffer Pointer A[31–16]
Tx Data Buffer Pointer A[15–0]
DEF
9
DATA LENGTH
HB
8
LC
7
Description
RL
6
5
RC
2
UN
Ethernet Module
1
CSL
0
11-37