MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 329

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

13.5.21 Sync Delay Registers (P0SDR–P3SDR)
All bits in these registers are read/write and are cleared on hardware or software reset.
The PnSDR registers contain the frame sync delay bits for each of the four ports on the MCF5272.
Freescale Semiconductor
15–14
13–10
Bits
9–0
Reset
Field FSW1 FSW0
Addr
R/W
FSW[1–0]
Name
SD
—
15
If a sync delay value of 0 is specified, that is, PnSDR[SD] = 0x000, then the
programmable delay block is transparent. When bypassed, the input frame
sync passes directly to the output, making the frame-sync-width function
defined by PnSDR[FSW] unavailable.
The 8-bit frame-sync-width should not be confused with long frame sync
mode. The PLIC only supports short frame sync in IDL8 and IDL10 bit
modes for interfacing to external transceivers.
Frame sync width. Sets the width, in clock cycles, of the output frame sync pulse.
00 Frame sync width = 1
01 Frame sync width = 2
10 Frame sync width = 8
11 Frame sync width = 16
Reserved, should be cleared.
Sync delay. Range: 0–1023. Sets the delay, in DCL clock cycles, for DFSC3–DFSC0. The delay period
should be doubled in GCI mode because GCI has two clock cycles per data bit. See
Timing
14
MCF5272 ColdFire
MBAR + 0x394 (P0SDR); 0x396 (P1SDR); 0x398 (P2SDR); 0x39A (P3SDR)
13
Generator,” for further information.
Figure 13-33. Sync Delay Registers (P0SDR–P3SDR)
Table 13-16. P0SDR–P3SDR Field Descriptions
—
®
Integrated Microprocessor User’s Manual, Rev. 3
10
0000_0000_0000_0000
9
NOTE
Read/Write
Description
SD
Physical Layer Interface Controller (PLIC)
Section 13.3, “PLIC
0
13-33