MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 202

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

SDRAM Controller
In
9.9
When some SDRAM devices (such as 4 x 8 bit wide SDRAMs) are used, the SDCLK and other control
signals are more loaded than data signals. In normal MCF5272 operation, the write data and all other
control signals change with the positive edge of SDCLK. Large capacitive loads on SDCLK can cause long
delays on SDCLK, possibly causing SDRAM hold-time violations during writes. The clock may arrive at
the same time as the write data.
The write data setup time to SDCLK edge may not meet device requirements at the SDRAM. This timing
issue cannot be solved by reducing the SDCLK frequency. SDCLK must be delayed further to meet
setup/hold margin on the SDRAM data input. Setting INV provides a 180° phase shift and moves the
positive clock edge far beyond the data edge.
9-12
Table
9-13, the timing configuration is RTP = 61, RC = negligible, RCD = 0, RP = 0, and CLT = 1.
Solving Timing Issues with SDCR[INV]
Internal CLK
Data bus
SDCLK
Figure 9-5. Example Setup Time Violation on SDRAM Data Input during Write
Single-beat read Page miss
Single-beat
longword read
Single-beat write Page miss
Single-beat
longword write
Burst read
Burst write
Table 9-13. SDRAM Controller Performance, 16-Bit Port, (RCD=0, RP=0)
MCF5272 ColdFire
SDRAM Access
Page hit
Page miss
Page hit
Page hit
Page miss
Page hit
Page miss
Page hit
Page miss
Page hit
®
Data setup delay
External delay of SDCLK
Integrated Microprocessor User’s Manual, Rev. 3
7
5
5-1-1-1-1-1-1-1 = 12
5
7-1
5-1
3
5-1
3-1
7-1-1-1-1-1-1-1 = 14
5-1-1-1-1-1-1-1 = 12
3-1-1-1-1-1-1-1 = 10
REG = 0, INV = 0
Number of System Clock Cycles
8
6
8-1
6-1
5
3
5-1
3-1
8-1-1-1-1-1-1-1 = 15
6-1-1-1-1-1-1-1 = 13
5-1-1-1-1-1-1-1 = 12
3-1-1-1-1-1-1-1 = 10
REG = 1, INV = 0
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