MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 167

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

6.2.5
The power management register (PMR),
including low-power sleep, low-power stop, and powering down individual on-chip modules.
Table 6-5
Freescale Semiconductor
11, 3
10, 2
Bits
9, 1
8, 0
Address
HWTEN
RPVEN
EXTEN
SUVEN
Fields
Reset
Reset
Reset
Reset
HWT,
RPV,
SUV,
describes PMR fields.
EXT,
Field BDMPDN
Field DMAPDN PWMPDN QSPIPDN TIMERPDN GPIOPDN USBPDN UART1PDN UART0PDN
Field
Field
R/W
R/W
R/W
R/W
Power Management Register (PMR)
Hardware watchdog timeout. This bit is set when the hardware watchdog timer has reached its
programmed timeout value. If HWTEN is also set, the bus cycle is terminated with an access error
exception.
Read protect violation. This bit is set when a read access is attempted to an area for which the chip select
is set to write only. If RPVEN is also set, the bus cycle is terminated with an access error exception.
External transfer error. This bit is set when an external transfer error is reported to the SIM on TEA. If
EXTEN is also set, the bus cycle is terminated with an access error exception.
Supervisor/user violation. This bit is set when a user mode access is attempted to an area for which the
chip select is set to supervisor only. If SUVEN is also set, the bus cycle is terminated with an access error
exception.
31
23
15
7
MCF5272 ColdFire
—
30
22
6
Figure 6-5. Power Management Register (PMR)
Table 6-4. SPR Field Descriptions (continued)
MOS
®
21
5
—
Integrated Microprocessor User’s Manual, Rev. 3
Figure
—
R/W, Supervisor mode only
R/W, Supervisor mode only
R/W, Supervisor mode only
R/W, Supervisor mode only
SLPEN
6-5, is used to control the various low-power options
20
4
MBAR+0x008
0000_0000
0000_0000
0000_0000
0000_0000
Description
27
19
11
3
ENETPDN
USBWK
26
18
10
—
UART1WK
PLIPDN
System Integration Module (SIM)
25
17
9
DRAMPDN
UART0WK
24
16
8
0
6-7