MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 307

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

13.2.5.3
There are a number of control mechanisms for the periodic and aperiodic interrupts on the PLIC.
13.3
13.3.1
The PLIC clock generator employs a completely digital, synchronous design which can be used to
synthesize a new clock by multiplying an incoming reference clock. This clock generator is not a PLL—it
has no VCO or phase comparator.
The frequency multiplication factor is always an integral power of two between 2 and 256 inclusive. The
amount of phase jitter exhibited by the synthesized clock increases as the synthesized clock frequency
approaches CLKIN’s frequency. As a general guide, the maximum generated DCL should be no greater
than one-twentieth of CLKIN’s frequency. Therefore, given a CLKIN of 66 MHz, the maximum frequency
which can be synthesized with acceptable jitter is approximately 3.3 MHz.
The clock generator uses a 14-bit counter to divide CLKIN. This limits the reference clock’s minimum
frequency to CLKIN divided by 16,384.
To summarize these two points:
The control of the clock generator block is provided through the PCSR register detailed in
“Clock Select Register
The process is illustrated by this example. Suppose the following:
The appropriate reference clock is selected by programming PLCLKSEL[CKI1, CKI0],
“Clock Select Register
by PLCLKSEL[CMULT0-2]. The division ratio between the synthesized clock (GDCL), 1.024 MHz, and
the synthesized frame sync (Gen_FSC) must be set. (A Gen_FSC of 8 KHz is assumed). This division ratio
is selected by means of FDIV[2-0]. Finally, the clock generation block should be taken out of bypass by
setting PCSR[NBP].
Freescale Semiconductor
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Clearing the ON/OFF bit in the port configuration register,
Registers
affected port.
Clearing the enable bits, ENB1 or ENB2, in the port configuration register masks the periodic
transmit and receive interrupts associated with the respective B1 or B2 channel.
Specific interrupt enables are provided in each port’s ICR. This includes a port interrupt enable, IE,
which masks all periodic and aperiodic interrupts. In addition, there are interrupt enables for
specific conditions. These are listed in
(P0ICR–P3ICR).”
Synthesized clock x 20 < CLKIN(Recommended)
Reference clock > CLKIN / 16,384(Required)
CPU clock = 66 MHz
Reference clock = 64 KHz
Synthesized clock = 1.024 MHz
PLIC Timing Generator
Clock Synthesis
Interrupt Control
(P0CR–P3CR),” turns the port off and masks all periodic and aperiodic interrupts for the
MCF5272 ColdFire
(PCSR).”
(PCSR).” The multiplication factor is 16 (1.024 MHz / 64 KHz) and is specified
®
Integrated Microprocessor User’s Manual, Rev. 3
Section 13.5.9, “Interrupt Configuration Registers
Section 13.5.7, “Port Configuration
Physical Layer Interface Controller (PLIC)
Section 13.5.22,
Section 13.5.22,
13-11