MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 477

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

21.3
The TAP controller is a synchronous state machine that controls JTAG logic and interprets the sequence
of logical values on TMS. The value adjacent to each arrow in the state machine in
the value of TMS sampled on the rising edge of TCK. For a description of the TAP controller states, refer
to the IEEE 1149.1 document.
Freescale Semiconductor
MTMOD
TDI/DSI
DSCLK
Signal
TRST/
TAP Controller
Test and debug data in. Input provided for loading serial data port shift registers (boundary-scan, bypass, and
instruction registers). Shifting in of data depends on the state of the JTAG controller state machine and the
instruction currently in the instruction register. Data is shifted in on the rising edge of TCK.
JTAG test reset. TRST asynchronously resets the JTAG TAP logic when low.
Freescale test mode select. Negating MTMOD enables JTAG mode; asserting it enables BDM mode.
MCF5272 ColdFire
Figure 21-2. TAP Controller State Machine
Table 21-1. JTAG Signals (continued)
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
IEEE 1149.1 Test Access Port (JTAG)
Figure 21-2
reflects
21-3