UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 817

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
3rd Edition
Remark “Classification” in the above table classifies revisions as follows.
Edition
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d):
Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Modification of Related Documents
Modification of description in 1.1 Features
Modification of Caution 1 in 1.3.3 78K0/KB2-L and 1.3.4 78K0/KC2-L
Modification of Caution 1 in 1.4.3 78K0/KB2-L and 1.4.4 78K0/KC2-L
Modification of description in 1.5 Outline of Functions
Modification of Table 3-6 Special Function Register List: 78K0/KY2-L to Table 3-9
Special Function Register List: 78K0/KC2-L
Modification of Table 4-10 Setting Functions of P21/ANI1/AMP0OUT/PGAIN Pin
Addition of description to 4.3 (5) Port output mode register 6 (POM6)
Addition of Caution 5 to Table 4-12 Settings of Port Mode Register and Output Latch
When Using Alternate Function (78K0/KY2-L) (1/2)
Addition of Caution 5 to Table 4-13 Settings of Port Mode Register and Output Latch
When Using Alternate Function (78K0/KA2-L) (1/2)
Addition of Caution 1 to Figure 5-8 Format of Main OSC Control Register (MOC)
Addition of Caution 1 to Figure 5-12 Format of Peripheral Enable Register 0 (PER0)
Modification of Figure 5-16 Clock Generator Operation When Power Supply Voltage Is
Turned On, (When LVI Default Start Function Stopped Is Set (Option Byte: LVISTART
= 0)) and Figure 5-17 Clock Generator Operation When Power Supply Voltage Is
Turned On (When LVI Default Start Function Enabled Is Set (Option Byte: LVISTART
= 1))
Modification of Figure 7-2 Block Diagram of 8-Bit Timer 51 (78K0/KY2-L, 78K0/KA2-L)
Addition of the port mode register 4 (PM4) and the port register 4 (P4) to Table 10-1
Configuration of Real-Time Counter
Addition of Caution 1 to Figure 10-2 Format of Peripheral Enable Register 0 (PER0)
Addition of the port mode register 4 (PM4) and the port register 4 (P4) to 10.3 Registers
Controlling Real-Time Counter
Modification of Figure 10-3 Format of Real-Time Counter Control Register 0 (RTCC0)
Modification of Figure 10-4 Format of Real-Time Counter Control Register 0 (RTCC1)
Modification of description in (7) Minute count register (MIN), (8) Hour count register
(HOUR), (9) Day count register (DAY), (11) Month count register (MONTH), (12) Year
count register (YEAR)
Modification of Figure 10-14 Format of Watch Error Correction Register (SUBCUD)
Modification of Figure 10-19 Procedure for Starting Operation of Real-Time Counter
Addition of 10.4.2 Shifting to STOP mode after starting operation
Modification of Figure 10-26 512 Hz, 16.384 kHz output Setting Procedure
Modification of (2) 2.7 V ≤ AV
Modification of Caution 3 in Figure 12-8 Format of Analog Input Channel Specification
Register (ADS)
REF
< 4.0 V in Table 12-2 A/D Conversion Time Selection
Description
APPENDIX C REVISION HISTORY
INTRODUCTION
CHAPTER 1
OUTLINE
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 7 8-BIT
TIMER/EVENT
COUNTERS 50 AND
51
CHAPTER 10 REAL-
TIME COUNTER
CHAPTER 12 A/D
CONVERTER
Chapter
(6/8)
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