UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 118

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
FF9DH
FF9EH
FF9FH
FFA0H
FFA1H
FFA2H
FFA3H
FFA4H
FFA5H
FFA6H
FFA7H
FFA8H
FFA9H
FFAAH
FFABH
FFACH
FFADH
FFAEH
FFAFH
FFB0H
FFB1H
FFB2H
FFB3H
FFB4H
FFB5H
FFB6H
FFB7H
FFB8H
FFB9H
Address
78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Notes 1. The value of this register is 00H immediately after a reset release but automatically changes to 80H after
Remark
RTCC0
RTCC1
OSCCTL
RCM
MCM
MOC
OSTC
OSTS
IICA
SVA0
IICACTL0
IICACTL1
IICAF0
IICAS0
RESF
IICWL
IICWH
RSUBC
SEC
MIN
HOUR
WEEK
DAY
MONTH
YEAR
SUBCUD
Symbol
2. The reset value of RESF varies depending on the reset source.
−
−
For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
oscillation accuracy stabilization of high-speed internal oscillator has been waited.
<MSTS0> <ALD0> <EXC0> <COI0> <TRC0> <ACKD0> <STD0> <SPD0>
<RTCE>
<WUP>
<WALE>
<MSTOP>
<IICE0> <LREL0> <WREL0> <SPIE0> <WTIM0> <ACKE0> <STT0> <SPT0>
<STCF> <IICBSY>
<EXCL
<RSTS>
YEAR
DEV
K>
80
−
7
0
0
0
−
−
0
−
−
−
−
−
0
0
0
0
0
0
SEC40 SEC20 SEC10
<WALI
MIN40
<OSC
YEAR
SEL>
E>
40
F6
−
−
−
−
−
−
−
−
6
0
0
0
0
0
0
0
0
0
0
0
0
Table 3-10. Special Function Register List: 78K0/KC2-L (5/6)
HOUR20 HOUR10 HOUR8 HOUR4 HOUR2 HOUR1
<RCLO
<CLD0> <DAD0> <SMC0> <DFC0>
<EXCL
DAY20 DAY10
MIN20
YEAR
KS>
E1>
20
F5
−
−
−
−
−
−
−
−
5
0
0
0
0
0
0
0
0
0
0
<WAFG> <RIFG>
MOST11 MOST13 MOST14 MOST15 MOST16
WDTRF
<RCLO
MONTH
SELS>
MIN10
<OSC
YEAR
E0>
10
F4
10
−
4
0
0
0
−
0
−
−
−
−
−
−
0
0
Bit No.
MONTH
YEAR8 YEAR4 YEAR2 YEAR1
AMPM
SEC8
DAY8
MIN8
F3
−
−
−
−
−
−
−
−
3
0
0
0
0
0
0
0
0
8
<XSEL> <MCS> <MCM0>
OSTS2 OSTS1 OSTS0
MONTH
WEEK4 WEEK2 WEEK1
<RSW
OSC>
SEC4
DAY4
MIN4
CT2
F2
−
−
−
−
−
−
−
−
2
0
0
0
0
0
4
<STCEN>
<RWST>
STOP>
MONTH
<AMP
HXT>
SEC2
DAY2
<LSR
MIN2
CT1
F1
−
1
0
−
0
−
0
−
−
−
−
−
2
<IICRSV>
MONTH
<RWAI
LVIRF
SEC1
DAY1
<RST
MIN1
OP>
CT0
T>
F0
0
0
0
−
0
0
−
−
−
−
−
−
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
−
−
CHAPTER 3 CPU ARCHITECTURE
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
√
√
√
√
√
√
√
√
√
√
√
Simultaneously
Number of Bits
Manipulated
−
−
−
8
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
−
−
−
−
−
−
−
−
80H
00H
0000H
Reset
After
FFH
FFH
00H
00H
00H
00H
80H
00H
05H
00H
00H
00H
00H
00H
00H
00H
00H
12H
00H
01H
01H
00H
00H
−
−
Note1
Note2
210, 640
211, 641
373
375
202
207
209
208
490
490
492
501
499
497
664
503
503
378
378
379
379
381
380
382
382
383
−
−
104