UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 814

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
2nd Edition
Remark “Classification” in the above table classifies revisions as follows.
Edition
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d):
Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Modification of Table 12-3 Setting Functions of P10/ANI8/AMP1-, P12/ANI10/AMP1+
Pins
Modification of Table 12-5 Setting Functions of P20/ANI0/AMP0-, P22/ANI2/AMP0+
Pins
Deletion of Caution 2 in 12.4.1 Basic operations of A/D converter
Modification of description of setting methods and deletion of Caution 2 in 12.4.3 (1) A/D
conversion operation
Modification of Figure 13-1 Block Diagram of Operational Amplifier
Addition of Remark to Figure 13-2 Format of Operational Amplifier 0 Control Register
(AMP0M) (Products with Operational Amplifier Only)
Modification of Figure 13-4 Format of A/D Port Configuration Register 0 (ADPC0)
Modification of Figure 13-5 Format of A/D Port Configuration Register 1 (ADPC1)
(78K0/KB2-L and 78K0/KC2-L Only)
Modification of Table 13-2 Setting Functions of P10/ANI8/AMP1-, P12/ANI10/AMP1+
Pins
Modification of Table 13-4 Setting Functions of P20/ANI0/AMP0-, P22/ANI2/AMP0+
Pins
Modification of Remark in Figure 14-4 Block Diagram of Serial Interface UART6
Addition of Note 3 to Figure 14-8 Format of Clock Selection Register 6 (CKSR6)
Modification of description in 14.3 (8) Port mode register 1 (PM1), port mode register 6
(PM6)
Modification of (1) 78K0/KY2-L and 78K0/KA2-L in Table 14-2 Relationship Between
Register Settings and Pins
Addition of 15.4.2 Setting transfer clock by using IICWL and IICWH registers
Modification of the mounted situation in the 78K0/KB2-L and 78K0/KC2-L
Modification of description in 16.3 (4) Port mode registers 1, 4, 6, 12 (PM1, PM4, PM6,
PM12)
Modification of and addition of Notes 3 and 4 to Table 16-3 SO1n Output Status
Modification of maskable interrupts (internal) in the 78K0/KB2-L and 78K0/KC2-L
Modification of Table 17-1 Interrupt Source List (1/2)
Modification of Table 17-2 Flags Corresponding to Interrupt Request Sources (1/2)
Modification of Caution in Figure 17-4 Format of Interrupt Request Flag Registers
(IF0L, IF0H, IF1L, IF1H) (78K0/KB2-L) to Figure 17-6 Format of Interrupt Request Flag
Registers (IF0L, IF0H, IF1L, IF1H) (48-pin products of 78K0/KC2-L)
Modification of Caution in Figure 17-9 Format of Interrupt Mask Flag Registers (MK0L,
MK0H, MK1L, MK1H) (78K0/KB2-L) to Figure 17-11 Format of Interrupt Mask Flag
Registers (MK0L, MK0H, MK1L, MK1H) (48-pin products of 78K0/KC2-L)
Description
APPENDIX C REVISION HISTORY
CHAPTER 12 A/D
CONVERTER
CHAPTER 13
OPERATIONAL
AMPLIFIERS
CHAPTER 14
SERIAL INTERFACE
UART6
CHAPTER 15
SERIAL INTERFACE
IICA
CHAPTER 16
SERIAL INTERFACES
CSI10 AND CSI11
CHAPTER 17
INTERRUPT
FUNCTIONS
Chapter
(3/8)
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