UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 107

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
FF8DH to
FF98H
FF99H
FF9AH to
FF9EH
FF9FH
FFA0H
FFA1H
FFA2H
FFA3H
FFA4H
FFA5H
FFA6H
FFA7H
FFA8H
FFA9H
FFAAH
FFABH
FFACH
FFADH
FFAEH
FFAFH
to FFB9H
FFBAH
FFBBH
FFBCH
FFBDH
FFBEH
FFBFH
Address
78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Notes 1. The reset value of WDTE is determined by setting of option byte.
Remark
WDTE
OSCCTL
RCM
MCM
MOC
OSTC
OSTS
IICA
SVA0
IICACTL0
IICACTL1
IICAF0
IICAS0
RESF
IICWL
IICWH
TMC00
PRM00
CRC00
TOC00
LVIM
LVIS
Symbol
2. The value of this register is 00H immediately after a reset release but automatically changes to 80H after
3. The reset value of RESF varies depending on the reset source.
4. 32-pin products only
5. The reset values of LVIM vary depending on the reset source and setting of option byte.
6. The reset value of LVIS varies depending on the reset source.
−
−
−
−
Note4
Table 3-8. Special Function Register List: 78K0/KA2-L (25-pin and 32-pin products) (4/5)
For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
oscillation accuracy stabilization of high-speed internal oscillator has been waited.
<MSTS0> <ALD0> <EXC0> <COI0> <TRC0> <ACKD0> <STD0> <SPD0>
<WUP>
<LVION>
<RSTS>
<MSTOP>
<IICE0> <LREL0> <WREL0> <SPIE0> <WTIM0> <ACKE0> <STT0> <SPT0>
<STCF> <IICBSY>
<EXCL
ES110
K>
−
7
−
−
−
0
0
0
−
−
0
−
−
−
0
0
0
0
<OSC
ES100
SEL>
<OSP
T00>
−
−
−
−
−
−
6
0
0
0
0
0
0
0
−
−
−
0
0
0
0
<CLD0> <DAD0> <SMC0> <DFC0>
ES010
<OSP
E00>
−
5
−
−
−
0
0
0
0
0
0
−
0
−
0
−
−
−
0
0
0
0
MOST11 MOST13 MOST14 MOST15 MOST16
WDTRF
ES000
TOC0
04
4
−
−
−
0
0
−
−
0
−
−
0
0
0
−
−
0
0
0
0
Bit No.
TMC003 TMC002 TMC001 <OVF00>
<LVS0
LVIS3
0>
−
−
−
−
−
−
3
0
0
0
0
0
0
0
−
−
−
0
0
0
CRC002 CRC001 CRC000
<XSEL> <MCS> <MCM0>
OSTS2 OSTS1 OSTS0
<LVR0
LVIS2
0>
−
2
−
−
−
0
0
−
0
−
0
−
0
0
−
−
0
<STCEN>
PRM001 PRM000
<LVIMD> <LVIF>
STOP>
<LSR
TOC0
LVIS1
01
−
−
−
−
−
−
1
0
0
0
0
−
−
−
<RSTO
<IICRSV>
LVIRF
<TOE0
LVIS0
P>
0>
−
−
−
0
−
0
0
−
0
0
−
−
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
−
−
−
−
CHAPTER 3 CPU ARCHITECTURE
1
−
−
−
√
√
√
√
√
−
−
−
√
√
√
√
−
−
−
−
−
√
√
√
√
√
√
Simultaneously
Number of Bits
Manipulated
−
−
√
√
√
√
−
√
√
√
−
√
√
√
√
√
√
8
√
√
√
√
√
√
√
√
√
16
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
9AH
80H
00H
Reset
After
1AH/
FFH
FFH
00H
00H
80H
00H
05H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Note5
Note6
−
−
−
−
Note
Note3
Note1
2
210, 640
211, 641
365
202
207
209
208
490
490
492
501
499
497
664
503
503
248
253
249
251
672
675
−
−
−
−
93