UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 520

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
15.4.2 Setting transfer clock by using IICWL and IICWH registers
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(1) Setting transfer clock on master side
(2) Setting IICWL and IICWH on slave side
Caution Note the minimum f
Remarks 1. Calculate the rise time (t
At this time, the optimal setting values of the IICWL and IICWH registers are as follows.
(The fractional parts of all setting values are rounded up.)
• When the fast mode
• When the normal mode
(The fractional parts of all setting values are truncated.)
• When the fast mode
• When the normal mode
Transfer clock =
IICWL =
IICWH = (
IICWL =
IICWH = (
IICWL = 1.3
IICWH = (1.2
IICWL = 4.7
IICWH = (5.3
operation frequency for serial interface IICA is determined according to the mode.
2. IICWL: IICA low-level width setting register
Fast mode:
Normal mode:
differ depending on the pull-up resistance and wire load.
IICWH: IICA high-level width setting register
t
t
f
F
R
PRS
:
:
Transfer clock
Transfer clock
:
Transfer clock
Transfer clock
IICWL + IICWH + f
μ
μ
μ
μ
s × f
s × f
0.52
0.47
s − t
s − t
SDAA0 and SCLA0 signal falling times (refer to CHAPTER 28 ELECTRICAL
SPECIFICATIONS)
SDAA0 and SCLA0 signal rising times (refer to CHAPTER 28 ELECTRICAL
SPECIFICATIONS)
Peripheral hardware clock frequency
0.48
0.53
PRS
PRS
R
R
− t
− t
f
f
F
F
PRS
PRS
) × f
) × f
× f
× f
PRS
f
PRS
− t
− t
PRS
PRS
= 3.5 MHz (min.)
= 1 MHz (min.)
PRS
PRS
R
R
operation frequency when setting the transfer clock. The minimum f
− t
− t
PRS
R
) and fall time (t
F
F
) × f
) × f
(t
R
PRS
PRS
+ t
F
)
F
) of the SDA0 and SCLA0 signals separately, because they
CHAPTER 15 SERIAL INTERFACE IICA
506
PRS