UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 536

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
SDAA0
SCLA0
Figure 15-26 shows the communication reservation timing.
Remark
Communication reservations are accepted via the timing shown in Figure 15-27. After bit 1 (STD0) of the IICA
status register 0 (IICAS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of the IICA
control register 0 (IICACTL0) to 1 before a stop condition is detected.
Figure 15-28 shows the communication reservation protocol.
SDAA0
SCLA0
SPD0
STD0
Hardware processing
Program processing
1
IICA:
STT0:
STD0: Bit 1 of IICA status register 0 (IICAS0)
SPD0: Bit 0 of IICA status register 0 (IICAS0)
Standby mode (Communication can be reserved by setting STT0 to 1 during this period.)
2
Figure 15-27. Timing for Accepting Communication Reservations
IICA shift register
Bit 1 of IICA control register 0 (IICACTL0)
3
STT0 = 1
Communi-
cation
reservation
4
Figure 15-26. Communication Reservation Timing
5
6
7
Generate by master device with bus mastership
8
9
Set SPD0
and
INTIICA0
CHAPTER 15 SERIAL INTERFACE IICA
Write to
IICA
Set
STD0
1
2
3
4
5
6
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