UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 183

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
PM7
Symbol
PM0
PM2
PM3
PM6
Note 2
Cautions 1. For 25-pin products, be sure to set bits 1 and 3 to 7 of PM0, bit 7 of PM2, and bits 2 to 7 of
Notes 1. 25-pin products only
PM27
PMmn
PM37
7
1
1
1
0
1
Notes 2, 3
Figure 4-32. Format of Port Mode Register (78K0/KA2-L (25-pin and 32-pin products)
2. 32-pin products only
3. If this pin is set as an analog input by using the ADPC0 and ADPC1 registers, be sure to set it to
4. For 25-pin products, clear it to 0.
5. For 32-pin products, clear it to 0.
2. For 32-pin products, be sure to set bits 0 and 3 to 7 of PM0, bits 2 to 7 of PM6, and bits 3 to 7
PM26
Output mode (output buffer on)
Input mode (output buffer off)
input mode.
PM36
PM6 to 1. Set P30 and P01 to output mode (PM30 = PM01 = 0) by using software after release
of reset.
of PM7 to 1. Set P30 to output mode (PM30 = 0) by using software after release of reset.
6
1
1
1
Note 3
PM25
PM35
5
1
1
1
Note 3
PM24
PM34
4
1
1
1
Note 3
PM23
PM33
3
1
1
1
Note 3
(m = 0, 2, 3, 6, 7; n = 0 to 7)
Pmn pin I/O mode selection
PM72
PM22
PM02
PM32
2
1
Notes 2, 3
Note 3
PM71
PM01
PM21
PM31 PM30
PM61
1
Notes 2, 3
Note 4
Note 3
PM00
PM20
PM70
PM60
Notes 4, 5
0
Notes 2, 3
Note 1
Note 3
CHAPTER 4 PORT FUNCTIONS
Address
FF20H
FF22H
FF23H
FF26H
FF27H
After reset
FFH
FFH
FFH
FFH
FFH
R/W
R/W
R/W
R/W
R/W
R/W
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