UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 506

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
15.3 Registers Controlling Serial Interface IICA
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(13) Bus status detector
Serial interface IICA is controlled by the following ten registers.
(1) IICA control register 0 (IICACTL0)
• IICA control register 0 (IICACTL0)
• IICA status register 0 (IICAS0)
• IICA flag register (IICAF0)
• IICA control register 1 (IICACTL1)
• IICA low-level width setting register (IICWL)
• IICA high-level width setting register (IICWH)
• Port input mode register 6 (PIM6)
• Port output mode register 6 (POM6)
• Port mode register 6 (PM6)
• Port register 6 (P6)
This register is used to enable/stop I
This register can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and
ACKE0 bits while IICE0 = 0 or during the wait period. These bits can be set at the same time when the IICE0 bit is
set from “0” to “1”.
Reset signal generation clears this register to 00H.
This circuit detects whether or not the bus is released by detecting start conditions and stop conditions.
However, as the bus status cannot be detected immediately following operation, the initial status is set by the
STCEN bit.
Remark
STT0 bit:
SPT0 bit:
IICRSV bit: Bit 0 of IICA flag register 0 (IICAF0)
IICBSY bit: Bit 6 of IICA flag register 0 (IICAF0)
STCF bit:
STCEN bit: Bit 1 of IICA flag register 0 (IICAF0)
Bit 1 of IICA control register 0 (IICACTL0)
Bit 0 of IICA control register 0 (IICACTL0)
Bit 7 of IICA flag register 0 (IICAF0)
2
C operations, set wait timing, and set other I
CHAPTER 15 SERIAL INTERFACE IICA
2
C operations.
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